Error-Correction in Flash Memories via Codes in the Ulam Metric

We consider rank modulation codes for flash memories that allow for handling arbitrary charge-drop errors. Unlike classical rank modulation codes used for correcting errors that manifest themselves as swaps of two adjacently ranked elements, the proposed \emph{translocation rank codes} account for more general forms of errors that arise in storage systems. Translocations represent a natural extension of the notion of adjacent transpositions and as such may be analyzed using related concepts in combinatorics and rank modulation coding. Our results include derivation of the asymptotic capacity of translocation rank codes, construction techniques for asymptotically good codes, as well as simple decoding methods for one class of constructed codes. As part of our exposition, we also highlight the close connections between the new code family and permutations with short common subsequences, deletion and insertion error-correcting codes for permutations, and permutation codes in the Hamming distance

플래시 메모리를 위한 양방향 비대칭 오류 정정 부호 및 간섭 완화 기법

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 2. 이정우.Recently, NAND multi-level cell (MLC) flash memories are now widely used due to low cost and high capacity. However, when the number of cell levels increases, cell-to-cell interference (C2CI) which shifts threshold voltage may degrades the error rate in reading process. There are several approaches to alleviate the errors caused by the threshold voltage shift and we discuss error correcting codes and message encoding schemes. First, we propose error correcting codes that are effective for multi-level cell flash memory and non-binary WOM (write once memory) codes. In particular, we focus on bidirectional error correction codes. The errors in MLC flash memories tend to be directional and limited-magnitude. Many related works focus on asymmetric errors, but bidirectional errors also occur because of the bidirectional interference and the adjustment of the hard-decision reference voltages. The code treats both upward and downward errors when the error magnitude in each direction differs. The maximum magnitudes of the upward error and downward error are lu and ld, respectively. One of proposed codes extends the technique of the distinct sum sets to the bidirectional error correction codes. The other code is bidirectional limited magnitude error correction codes based on modulo operation and uses non-binary conventional error correction codes. These proposed codes can reduce the parity size, and have better error correction performance than the conventional error correction codes when the code rate is equal. Furthermore, error correcting schemes for non-binary WOM codes are discussed. WOM codes is a coding scheme that allows information to be written in a memory cell multiple times without erasure, and conventional error correction codes cannot be directly applied to WOM codes. The advantages of the proposed methods are that these are practical and systematic codes, and the complexity of encoding and decoding processes are low. We also introduce effective error locating limited-magnitude parity check error correction codes for the MLC flash memory error with lower complexity. Second, we introduce coding schemes to lower the generated interferences by cell to cell interference. It is known that C2CI is caused by the threshold voltage change of neighbor cells in writing operation. The amount of threshold voltage change is proportional to the magnitude. To minimize the generated interference, the average magnitude needs to be decreased. We propose two new C2CI reduction coding schemes that adjust the average magnitude to reduce C2CI. The proposed coding scheme deals with q-ary message codes, and generates fixed length codes. Message codewords are divided into several blocks, and are modified by modulo addition with proper values to minimize the average magnitude. We also propose low energy Huffman codes based on entropy coding when the frequency of symbols is not distributed uniformly. This scheme produces variable-length codes without redundancy. We modified Huffman codes to minimize average number of high bits ('1' bits). We show that proposed codes generate optimal codewords which have minimum high bits with minimum average codeword length.Chapter 1 Introduction 1 1.1 Backgrounds 1 1.2 Scope and Organization 5 Chapter 2 MLC Flash Memory Interference and Mitigation Techniques for Reliability 9 2.1 MLC flash memory and interference 9 2.2 Signal processing based interference mitigation in MLC flash memories 15 2.3 WOM codes 22 2.4 Asymmetric limited-magitude error correction codes based on distinct sum set 27 Chapter 3 Error Correction Codes for Flash Memories 29 3.1 Introduction 29 3.2 Bidirectional error correction codes for non-binary WOM codes based on distinct sum sets 30 3.2.1 Bidirectional error correction codes based on distinct sum sets 30 3.2.2 Error correction coding schemes for WOM codes based on distinct sum sets 41 3.3 Bidirectional error correction codes for WOM codes based on modulo operation 44 3.3.1 Bidirectional error correction codes based on modulo operation 44 3.3.2 Performance simulation of bidirectional error correction codes based on modulo operation 54 3.3.3 Error correction coding schemes for WOM codes based on modulo operation 58 3.4 Performance of error correction coding schemes for WOM code 61 3.5 Error locating parity check codes for errors with limited magnitude 68 3.6 Summary 77 Chapter 4 On Interference Mitigating Codes for Multi-level Flash Memories 79 4.1 Introduction 79 4.2 The modeling of generated interference in flash memory 80 4.3 Coding schemes for interference mitigation 83 4.3.1 Minimum energy coding 83 4.3.2 Module shift coding 85 4.3.3 Low energy Huffman code 89 4.4 Performance analysis of proposed coding schemes 91 4.4.1 Performance analysis of ME codes 91 4.4.2 Performance analysis of MS codes 93 4.4.3 Performance of low-energy Huffman codes 97 4.4.4 C2CI reduction performance 99 4.5 Summary 102 Chapter 5 Conclusions 105 Appendix A 109 A.1 Performance analysis of MS coding with eta=2 case in chap. 4.4.2. 109 Bibliography 113 Abstract in Korean 120Docto

Storage Techniques in Flash Memories and Phase-change Memories

Non-volatile memories are an emerging storage technology with wide applica- tions in many important areas. This study focuses on new storage techniques for flash memories and phase-change memories. Flash memories are currently the most widely used type of non-volatile memory, and phase-change memories (PCMs) are the most promising candidate for the next-generation non-volatile memories. Like magnetic recording and optical recording, flash memories and PCMs have their own distinct properties, which introduce very interesting data storage problems. They include error correction, cell programming and other coding problems that affect the reliability and efficiency of data storage. Solutions to these problems can signifi- cantly improve the longevity and performance of the storage systems based on flash memories and PCMs. In this work, we study several new techniques for data storage in flash memories and PCMs. First, we study new types of error-correcting codes for flash memories – called error scrubbing codes –that correct errors by only increasing cell levels. Error scrubbing codes can correct errors without the costly block erasure operations, and we show how they can outperform conventional error-correcting codes. Next, we study the programming strategies for flash memory cells, and present an adaptive algorithm that optimizes the expected precision of cell programming. We then study data storage in PCMs, where thermal interference is a major challenge for data reliability. We present two new coding techniques that reduce thermal interference, and study their storage capacities and code constructions

Product Error-Correcting Codes That Span NAND-Flash Dies

NAND-flash memories include a matrix of pages. Each column of the matrix is located in one physical semiconductor die. Because errors are correlated such that they occur in groups within a die, error-correcting codes (ECC) are optimally constructed across dies (matrix rows), a principle known as cross-die design. A product ECC is a type of code that encodes rows to one parity and columns to another. Although the row-constituents of product codes are cross-die, the column-constituents are not so. This disclosure describes product ECCs where both constituent codes span semiconductor dies. The described cross-die product codes provide better performance for random errors while maintaining performance comparable to traditional codes for correlated errors, at nearly the same coding overhead. A page in error can be repaired in two unique ways, both of which are cross-die, thereby improving data reliability and speed of repair

Algorithms and Data Representations for Emerging Non-Volatile Memories

The evolution of data storage technologies has been extraordinary. Hard disk drives that fit in current personal computers have the capacity that requires tons of transistors to achieve in 1970s. Today, we are at the beginning of the era of non-volatile memory (NVM). NVMs provide excellent performance such as random access, high I/O speed, low power consumption, and so on. The storage density of NVMs keeps increasing following Moore’s law. However, higher storage density also brings significant data reliability issues. When chip geometries scale down, memory cells (e.g. transistors) are aligned much closer to each other, and noise in the devices will become no longer negligible. Consequently, data will be more prone to errors and devices will have much shorter longevity. This dissertation focuses on mitigating the reliability and the endurance issues for two major NVMs, namely, NAND flash memory and phase-change memory (PCM). Our main research tools include a set of coding techniques for the communication channels implied by flash memory and PCM. To approach the problems, at bit level we design error correcting codes tailored for the asymmetric errors in flash and PCM, we propose joint coding scheme for endurance and reliability, error scrubbing methods for controlling storage channel quality, and study codes that are inherently resisting to typical errors in flash and PCM; at higher levels, we are interested in analyzing the structures and the meanings of the stored data, and propose methods that pass such metadata to help further improve the coding performance at bit level. The highlights of this dissertation include the first set of write-once memory code constructions which correct a significant number of errors, a practical framework which corrects errors utilizing the redundancies in texts, the first report of the performance of polar codes for flash memories, and the emulation of rank modulation codes in NAND flash chips