Enhancing the EAST-ADL error model with HiP-HOPS semantics

EAST-ADL is a domain-specific modelling language for the engineering of automotive embedded systems. The language has abstractions that enable engineers to capture a variety of information about design in the course of the lifecycle — from requirements to detailed design of hardware and software architectures. The specification of the EAST-ADL language includes an error model extension which documents language structures that allow potential failures of design elements to be specified locally. The effects of these failures are then later assessed in the context of the architecture design. To provide this type of useful assessment, a language and a specification are not enough; a compiler-like tool that can read and operate on a system specification together with its error model is needed. In this paper we integrate the error model of EAST-ADL with the precise semantics of HiP-HOPS — a state-of-the-art tool that enables dependability analysis and optimization of design models. We present the integration concept between EAST-ADL structure and HiP-HOPS error propagation logic and its transformation into the HiP-HOPS model. Source and destination models are represented using the corresponding XML formats. The connection of these two models at tool level enables practical EAST-ADL designs of embedded automotive systems to be analysed in terms of dependability, i.e. safety, reliability and availability. In addition, the information encoded in the error model can be re-used across different contexts of application with the associated benefits for cost reduction, simplification, and rationalisation of dependability assessments in complex engineering designs

A Self Learning based Diagnosis of Faulty Configurable Logic Blocks (CLBs) in Field Programmable Gate Arrays (FPGA) Using Reconfiguration

In many areas of digital systems Field programmable gate arrays (FPGAs) are most important for designing. The main usesof FPGAs are, these are programmable, and faults can be easily diagnosed, once faulty locations are identified. The locationand identification of faults in FPGA has not yet been explored much. A methodology for the testing and diagnosis of faultsin FPGAs is presented based on automatic circuit reconfiguration. The proposed method imposes no hardware overhead.This method can also be used in fault-tolerant systems, in which a good functional circuit can be still mapped to a FPGAwith faulty elements, as long as the fault sites are known. The logic synthesis software assigns the Configurable Logic Block(CLB) resources without system designer intervention. It is very advantageous for the designer to understand certain CLBdetails, including the varying capabilities of the look-up tables (LUTs), the physical direction of the carry propagation, thenumber and distribution of the available flip-flops. FPGA consists of 25 Configurable Logic Blocks (CLB). Each CLB isassigned with an application. The inputs for CLB are applied from a file. There is also a fault file in which error CLBs arepresent. If there is error CLBs, those CLBs are replaced by the spare CLBs. Finally, the errors CLBs are corrected withproper inputs and modified bits are displayed. So efficiency is not reduced and configurability is done without replacing thefaulty components. This FPGA can tolerate not only single faults but also for multiple faults. The power analysis resultsprovided for fault free, stuck-at-1, stuck-at-0 faults in digital circuits validate the point that faulty circuits dissipates moreand hence draw more power.Key words: Configurable Logic Block (CLB), Power Dissipation, Fault Tolerance, Fault Diagnosis, Faults, Full adder (FA)

W-NINE: a two-stage emulation platform for mobile and wireless systems

More and more applications and protocols are now running on wireless networks. Testing the implementation of such applications and protocols is a real challenge as the position of the mobile terminals and environmental effects strongly affect the overall performance. Network emulation is often perceived as a good trade-off between experiments on operational wireless networks and discrete-event simulations on Opnet or ns-2. However, ensuring repeatability and realism in network emulation while taking into account mobility in a wireless environment is very difficult. This paper proposes a network emulation platform, called W-NINE, based on off-line computations preceding online pattern-based traffic shaping. The underlying concepts of repeatability, dynamicity, accuracy and realism are defined in the emulation context. Two different simple case studies illustrate the validity of our approach with respect to these concepts

Hamevol1.0: a C++ code for differential equations based on Runge-Kutta algorithm. An application to matter enhanced neutrino oscillation

We present a C++ implementation of a fifth order semi-implicit Runge-Kutta algorithm for solving Ordinary Differential Equations. This algorithm can be used for studying many different problems and in particular it can be applied for computing the evolution of any system whose Hamiltonian is known. We consider in particular the problem of calculating the neutrino oscillation probabilities in presence of matter interactions. The time performance and the accuracy of this implementation is competitive with respect to the other analytical and numerical techniques used in literature. The algorithm design and the salient features of the code are presented and discussed and some explicit examples of code application are given.Comment: 18 pages, Late