A Survey on Wireless Sensor Network Security

Wireless sensor networks (WSNs) have recently attracted a lot of interest in the research community due their wide range of applications. Due to distributed nature of these networks and their deployment in remote areas, these networks are vulnerable to numerous security threats that can adversely affect their proper functioning. This problem is more critical if the network is deployed for some mission-critical applications such as in a tactical battlefield. Random failure of nodes is also very likely in real-life deployment scenarios. Due to resource constraints in the sensor nodes, traditional security mechanisms with large overhead of computation and communication are infeasible in WSNs. Security in sensor networks is, therefore, a particularly challenging task. This paper discusses the current state of the art in security mechanisms for WSNs. Various types of attacks are discussed and their countermeasures presented. A brief discussion on the future direction of research in WSN security is also included.Comment: 24 pages, 4 figures, 2 table

Efficient and Secure ECDSA Algorithm and its Applications: A Survey

Public-key cryptography algorithms, especially elliptic curve cryptography (ECC)and elliptic curve digital signature algorithm (ECDSA) have been attracting attention frommany researchers in different institutions because these algorithms provide security andhigh performance when being used in many areas such as electronic-healthcare, electronicbanking,electronic-commerce, electronic-vehicular, and electronic-governance. These algorithmsheighten security against various attacks and the same time improve performanceto obtain efficiencies (time, memory, reduced computation complexity, and energy saving)in an environment of constrained source and large systems. This paper presents detailedand a comprehensive survey of an update of the ECDSA algorithm in terms of performance,security, and applications

Improved Secure and Low Computation Authentication Protocol for Wireless Body Area Network with ECC and 2d Hash Chain

Since technologies have been developing rapidly, Wireless Body Area Network (WBAN) has emerged as a promising technique for healthcare systems. People can monitor patients’ body condition and collect data remotely and continuously by using WBAN with small and compact wearable sensors. These sensors can be located in, on, and around the patient’s body and measure the patient’s health condition. Afterwards sensor nodes send the data via short-range wireless communication techniques to an intermediate node. The WBANs deal with critical health data, therefore, secure communication within the WBAN is important. There are important criteria in designing a security protocol for a WBAN. Sensor nodes in a WBAN have limited computation power, battery capacity, and limited memory. Therefore, there have been many efforts to develop lightweight but secure authentication protocols. In this thesis, a computationally efficient authentication protocol based on Elliptic Curves Cryptography (ECC) and 2D hash chain has been proposed. This protocol can provide high level security and require significantly low computation power on sensor nodes. In addition, a novel key selection algorithm has been proposed to improve efficiency of key usage and reduce computation cost. For this protocol, ECC is used for key exchange and key encryption. The scheme encrypts a key with ECC to create a pair of points and uses this pair of points as keys for an intermediate node and sensor nodes. 2D hash chain technique is used for generating 2D key pool for authentication procedure. This technique can generate many keys efficiently and effectively with hash functions. For security part, this protocol provides essential security features including mutual authentication, perfect forward security, session key establishment, and etc., while providing high level security. In experimental results, this protocol reduced sensor nodes’ computation cost significantly by using combination of ECC and 2D hash chain. Moreover, the computation cost on the intermediate node has been reduced to 48.2% of the existing approach by the new key selection algorithm at an initial authentication. After the initial authentication, the intermediate node’s computation cost is further reduced to 47.1% of the initial authentication by eliminating synchronization phase. In addition, communication cost which is the total packet size of all messages is 1280-bits, which is 5392-bits smaller than the existing approach, for entire authentication and after the initial authentication the cost is reduced to 768-bits

Energy Efficient Hardware Design for Securing the Internet-of-Things

The Internet of Things (IoT) is a rapidly growing field that holds potential to transform our everyday lives by placing tiny devices and sensors everywhere. The ubiquity and scale of IoT devices require them to be extremely energy efficient. Given the physical exposure to malicious agents, security is a critical challenge within the constrained resources. This dissertation presents energy-efficient hardware designs for IoT security. First, this dissertation presents a lightweight Advanced Encryption Standard (AES) accelerator design. By analyzing the algorithm, a novel method to manipulate two internal steps to eliminate storage registers and replace flip-flops with latches to save area is discovered. The proposed AES accelerator achieves state-of-art area and energy efficiency. Second, the inflexibility and high Non-Recurring Engineering (NRE) costs of Application-Specific-Integrated-Circuits (ASICs) motivate a more flexible solution. This dissertation presents a reconfigurable cryptographic processor, called Recryptor, which achieves performance and energy improvements for a wide range of security algorithms across public key/secret key cryptography and hash functions. The proposed design employs circuit techniques in-memory and near-memory computing and is more resilient to power analysis attack. In addition, a simulator for in-memory computation is proposed. It is of high cost to design and evaluate new-architecture like in-memory computing in Register-transfer level (RTL). A C-based simulator is designed to enable fast design space exploration and large workload simulations. Elliptic curve arithmetic and Galois counter mode are evaluated in this work. Lastly, an error resilient register circuit, called iRazor, is designed to tolerate unpredictable variations in manufacturing process operating temperature and voltage of VLSI systems. When integrated into an ARM processor, this adaptive approach outperforms competing industrial techniques such as frequency binning and canary circuits in performance and energy.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147546/1/zhyiqun_1.pd

Forward error correction for molecular communications

Communication between nanoscale devices is an area of considerable importance as it is essential that future devices be able to form nanonetworks and realise their full potential. Molecular communication is a method based on diffusion, inspired by biological systems and useful over transmission distances in the nm to μm range. The propagation of messenger molecules via diffusion implies that there is thus a probability that they can either arrive outside of their required time slot or ultimately, not arrive at all. Therefore, in this paper, the use of a error correcting codes is considered as a method of enhancing the performance of future nanonetworks. Using a simple block code, it is shown that it is possible to deliver a coding gain of ∼1.7 dB at transmission distances of . Nevertheless, energy is required for the coding and decoding and as such this paper also considers the code in this context. It is shown that these simple error correction codes can deliver a benefit in terms of energy usage for transmission distances of upwards of for receivers of a radius

Novel Area-Efficient and Flexible Architectures for Optimal Ate Pairing on FPGA

While FPGA is a suitable platform for implementing cryptographic algorithms, there are several challenges associated with implementing Optimal Ate pairing on FPGA, such as security, limited computing resources, and high power consumption. To overcome these issues, this study introduces three approaches that can execute the optimal Ate pairing on Barreto-Naehrig curves using Jacobean coordinates with the goal of reaching 128-bit security on the Genesys board. The first approach is a pure software implementation utilizing the MicroBlaze processor. The second involves a combination of software and hardware, with key operations in $F_{p}$ and $F_{p^{2}}$ being transformed into IP cores for the MicroBlaze. The third approach builds on the second by incorporating parallelism to improve the pairing process. The utilization of multiple MicroBlaze processors within a single system offers both versatility and parallelism to speed up pairing calculations. A variety of methods and parameters are used to optimize the pairing computation, including Montgomery modular multiplication, the Karatsuba method, Jacobean coordinates, the Complex squaring method, sparse multiplication, squaring in $G_{\phi 6}F_{p^{12}}$, and the addition chain method. The proposed systems are designed to efficiently utilize limited resources in restricted environments, while still completing tasks in a timely manner.Comment: 13 pages, 8 figures, and 5 table