Density Evolution for Deterministic Generalized Product Codes with Higher-Order Modulation

Generalized product codes (GPCs) are extensions of product codes (PCs) where coded bits are protected by two component codes but not necessarily arranged in a rectangular array. It has recently been shown that there exists a large class of deterministic GPCs (including, e.g., irregular PCs, half-product codes, staircase codes, and certain braided codes) for which the asymptotic performance under iterative bounded-distance decoding over the binary erasure channel (BEC) can be rigorously characterized in terms of a density evolution analysis. In this paper, the analysis is extended to the case where transmission takes place over parallel BECs with different erasure probabilities. We use this model to predict the code performance in a coded modulation setup with higher-order signal constellations. We also discuss the design of the bit mapper that determines the allocation of the coded bits to the modulation bits of the signal constellation.Comment: invited and accepted paper for the special session "Recent Advances in Coding for Higher Order Modulation" at the International Symposium on Turbo Codes & Iterative Information Processing, Brest, France, 201

Nouvelles stratégies de concaténation de codes séries pour la réduction du seuil d’erreur dans le contrôle de parité à faible densité et dans les turbo codes produits

This paper presents a novel multiple serial code concatenation (SCC) strategy to combat the error-floor problem in iterated sparse graph-based error correcting codes such as turbo product-codes (TPC) and low-density parity-check (LDPC) codes. Although SCC has been widely used in the past to reduce the error-floor in iterative decoders, the main stumbling block for its practical application in high-speed communication systems has been the need for long and complex outer codes. Alternative, short outer block codes with interleaving have been shown to provide a good tradeoff between complexity and performance. Nevertheless, their application to next-generation high-speed communication systems is still a major challenge as a result of the careful design of long complex interleavers needed to meet the requirements of these applications. The SCC scheme proposed in this work is based on the use of short outer block codes. Departing from techniques used in previous proposals, the long outer code and interleaver are replaced by a simple block code combined with a novel encoding/decoding strategy. This allows the proposed SCC to provide a better tradeoff between performance and complexity than previous techniques. Several application examples showing the benefits of the proposed SCC are described. Particularly, a new coding scheme suitable for high-speed optical communication is introduced.Fil: Morero, Damián Alfonso. Universidad Nacional de Cordoba. Facultad de Ciencias Exactas, Fisicas y Naturales; ArgentinaFil: Hueda, Mario Rafael. Universidad Nacional de Cordoba. Facultad de Ciencias Exactas, Fisicas y Naturales; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Córdoba; Argentin

Stall Pattern Avoidance in Polynomial Product Codes

Product codes are a concatenated error-correction scheme that has been often considered for applications requiring very low bit-error rates, which demand that the error floor be decreased as much as possible. In this work, we consider product codes constructed from polynomial algebraic codes, and propose a novel low-complexity post-processing technique that is able to improve the error-correction performance by orders of magnitude. We provide lower bounds for the error rate achievable under post processing, and present simulation results indicating that these bounds are tight.Comment: 4 pages, 2 figures, GlobalSiP 201

FPGA implementation of Reed Solomon codec for 40Gbps Forward Error Correction in optical networks

Reed-Solomon error correcting codes (RS codes) are widely used in communication and data storage systems to recover data from possible errors that occur during data transfer. A growing application of RS codes is Forward Error Correction (FEC) in the Optical Network (OTN G.709), which uses RS(255,239) to support the OTU-3 (43.018 Gbps) standard. There have been considerable efforts in the area of RS architecture for ASIC implementation. However, there appears to be little reported work on efficient RS codec (encoder and decoder) for Field Programmable Gate Arrays (FPGAs), which has increasing interests in industry. This thesis investigates the implementation and design methodology of the RS(255,239) codec on FPGAs. A portable VHDL code is developed and synthesized for Xilinx\u27s Virtex4 and Altera\u27s StratixII. The FPGA architectures are analyzed and the required design methodologies are adopted to efficiently utilize the available resources. Unfortunately, due to the fixed size of FPGA devices, the RS decoder is not only constrained by the required timing of the system, but also by the size of the targeted device. This research will facilitate the decision-making process for selecting a reconfigurable device for a RS decoder, implementing the Berlekamp-Massey Algorithm

Approaching Capacity at High-Rates with Iterative Hard-Decision Decoding

A variety of low-density parity-check (LDPC) ensembles have now been observed to approach capacity with message-passing decoding. However, all of them use soft (i.e., non-binary) messages and a posteriori probability (APP) decoding of their component codes. In this paper, we show that one can approach capacity at high rates using iterative hard-decision decoding (HDD) of generalized product codes. Specifically, a class of spatially-coupled GLDPC codes with BCH component codes is considered, and it is observed that, in the high-rate regime, they can approach capacity under the proposed iterative HDD. These codes can be seen as generalized product codes and are closely related to braided block codes. An iterative HDD algorithm is proposed that enables one to analyze the performance of these codes via density evolution (DE).Comment: 22 pages, this version accepted to the IEEE Transactions on Information Theor