Routing algorithm for multirate circuit switching in quantized Clos network.

by Wai-Hung Kwok.Thesis (M.Phil.)--Chinese University of Hong Kong, 1997.Chapter 1 --- Introduction --- p.1Chapter 2 --- Preliminaries - Routing in Classical Circuit Switching Clos Net- work --- p.9Chapter 2.1 --- Formulation of route assignment as bipartite multigraph coloring problem --- p.10Chapter 2.1.1 --- Definitions --- p.10Chapter 2.1.2 --- Problem formulation --- p.11Chapter 2.2 --- Edge-coloring of bipartite graph --- p.12Chapter 2.3 --- Routing algorithm - Paull's matrix --- p.15Chapter 3 --- Principle of Routing Algorithm --- p.18Chapter 3.1 --- Definitions --- p.18Chapter 3.1.1 --- Bandwidth quantization --- p.18Chapter 3.1.2 --- Connection splitting --- p.20Chapter 3.2 --- Non-blocking conditions --- p.20Chapter 3.2.1 --- Rearrangeably non-blocking condition --- p.21Chapter 3.2.2 --- Strictly non-blocking condition --- p.22Chapter 3.3 --- Formulation of route assignment as weighted bipartite multigraph coloring problem --- p.23Chapter 3.4 --- Edge-coloring of weighted bipartite multigraph with edge splitting --- p.25Chapter 3.4.1 --- Procedures --- p.25Chapter 3.4.2 --- Example --- p.27Chapter 3.4.3 --- Validity of the color rearrangement procedure --- p.29Chapter 4 --- Routing Algorithm --- p.32Chapter 4.1 --- Capacity allocation matrix --- p.32Chapter 4.2 --- Connection setup --- p.34Chapter 4.2.1 --- Non-splitting stage --- p.35Chapter 4.2.2 --- Splitting stage --- p.36Chapter 4.2.3 --- Recursive rearrangement stage --- p.37Chapter 4.3 --- Connection release --- p.40Chapter 4.4 --- Realization of route assignment in packet level --- p.42Chapter 5 --- Performance Studies --- p.45Chapter 5.1 --- External blocking probability --- p.45Chapter 5.1.1 --- Reduced load approximation --- p.46Chapter 5.1.2 --- Comparison of external blocking probabilities --- p.48Chapter 5.2 --- Connection splitting probability --- p.50Chapter 5.3 --- Recursive rearrangement probability --- p.50Chapter 6 --- Conclusions --- p.5

Switching techniques for broadband ISDN

The properties of switching techniques suitable for use in broadband networks have been investigated. Methods for evaluating the performance of such switches have been reviewed. A notation has been introduced to describe a class of binary self-routing networks. Hence a technique has been developed for determining the nature of the equivalence between two networks drawn from this class. The necessary and sufficient condition for two packets not to collide in a binary self-routing network has been obtained. This has been used to prove the non-blocking property of the Batcher-banyan switch. A condition for a three-stage network with channel grouping and link speed-up to be nonblocking has been obtained, of which previous conditions are special cases. A new three-stage switch architecture has been proposed, based upon a novel cell-level algorithm for path allocation in the intermediate stage of the switch. The algorithm is suited to hardware implementation using parallelism to achieve a very short execution time. An array of processors is required to implement the algorithm The processor has been shown to be of simple design. It must be initialised with a count representing the number of cells requesting a given output module. A fast method has been described for performing the request counting using a non-blocking binary self-routing network. Hardware is also required to forward routing tags from the processors to the appropriate data cells, when they have been allocated a path through the intermediate stage. A method of distributing these routing tags by means of a non-blocking copy network has been presented. The performance of the new path allocation algorithm has been determined by simulation. The rate of cell loss can increase substantially in a three-stage switch when the output modules are non-uniformly loaded. It has been shown that the appropriate use of channel grouping in the intermediate stage of the switch can reduce the effect of non-uniform loading on performance

Design techniques to enhance low-power wireless communication soc with reconfigurability and wake up radio

Nowadays, Internet of things applications are increasing, and each end-node has more demanding requirements such as energy efficiency and speed. The thesis proposes a heterogeneous elaboration unit for smart power applications, that consists of an ultra-low-power microcontroller coupled with a small (around 1k equivalent gates) soft-core of embedded FPGA. This digital system is implemented in 90-nm BCD technology of STMicroelectronics, and through the analysis presented in this thesis proves to have good performance in terms of power consumption and latency. The idea is to increase the system performance exploiting the embedded FPGA to managing smart power tasks. For the intended applications, a remarkable computational load is not required, it is just required the implementation of simple finite state machines, since they are event-driven applications. In this way, while the microcontroller deals with other system computations such as high-level communications, the eFPGA can efficiently manage smart power applications. An added value of the proposed elaboration unit is that a soft-core approach is applied to the whole digital system including the eFPGA, and hence, it is portable to different technologies. On the other hand, the configurability improvement has a straightforward drawback of about a 20–27% area overhead. The eFPGA usage to manage smart power applications, allows the system to reduce the required energy per task from about 400 to around 800 times compared to a processor implementation. The eFPGA utilization improves also the latency performance of the system reaching from 8 to 145 times less latency in terms of clock cycles. The thesis also introduces the architecture of a nano-watt wake-up radio integrated circuit implemented in 90-nm BCD technology of STMicroelectronics. The wake-up radio is an auxiliary always-on radio for medium-range applications that allows the IoT end-nodes to drastically reduce the power consumption during the node idle-listening communication phase

Devices and networks for optical switching

This thesis is concerned with some aspects of the application of optics to switching and computing. Two areas are dealt with: the design of switching networks which use optical interconnects, and the development and application of the t-SEED optical logic device. The work on optical interconnects looks at the multistage interconnection network which has been proposed as a hybrid switch using both electronics and optics. It is shown that the architecture can be mapped from one dimensional to two dimensional format, so that the machine makes full use of the space available to the optics. Other mapping rules are described which allow the network to make optimum use of the optical interconnects, and the endpoint is a hybrid optical-electronic machine which should be able to outperform an all-electronic equivalent. The development of the t-SEED optical logic device is described, which is the integration of a phototransistor with a multiple quantum well optical modulator. It is found to be important to have the modulator underneath rather than on top of the transistor to avoid unwanted thyristor action. In order for the transistor to have a high gain the collector must have a low doping level, the exit window in the substrate must be etched all the way to the emitter layer, and the etch must not damage the emitter-base junction. A real optical gain of 1.6 has been obtained, which is higher than has ever been reached before but is not as high as should be possible. Improvements to the device are suggested. A new model of the Fabry-Perot cavity is introduced which helps considerably in the interpretation of experimental measurements made on the quantum well modulators. Also a method of improving the contrast of the multiple quantum well modulator by grading the well widths is proposed which may find application in long wavelength transmission modulators. Some systems which make use of the t-SEED are considered. It is shown that the t-SEED device has the right characteristics for use as a neuron element in the optical implementation of a neural network. A new image processing network for clutter removal in binary images is introduced which uses the t-SEED, and a brief performance analysis suggests that the network may be superior to an all-electronic machine

Constructive Formal Control Synthesis through Abstraction and Decomposition

Control synthesis is the problem of automatically constructing a control strategy that induces a system to exhibit a declared behavior. Synthesis algorithms vary widely across different classes of system dynamics and specifications.While continuous optimization has traditionally been used to construct stabilizing controllers for physical systems modeled with differential equations, temporal logic synthesis for finite state machines heavily leverages discrete algorithms and data structures.Hybrid systems are a class of systems that exhibit both continuous and discrete behaviors, which are necessary to capture phenomena such as impacts for legged robots and congestion shockwaves in freeways. Tractable control synthesis remains elusive because hybrid systems violate many of the fundamental topological assumptions made by prior algorithms for purely continuous or discrete systems.This thesis exploits compositionality and system structure to provide a suite of algorithmic and theoretical techniques to tackle acute computational bottlenecks in hybrid control synthesis.The first half of this thesis provides a framework for engineers to model control systems and construct algorithmic pipelines for control synthesis.By explicitly capturing system structure, this framework gives users the flexibility to rapidly iterate over and leverage a library of optimizations for control synthesis.We demonstrate this framework in the context of abstraction-based control, a synthesis workflow that translates continuous systems into finite state machines by throwing away high precision information. Different optimization techniques such as multi-scale grids, lazy abstraction, and decomposed synthesis, can all be expressed as modifications to a computational pipeline. We demonstrate computational gains while synthesizing safe motion primitives for numerous robotic examples.The second half addresses distributed control synthesis where multiple controllers act as agents that seek to jointly satisfy a specification and are restricted by some communication topology. We introduce parametric assume-guarantee contracts as a formalism to derive guarantees about the closed loop behavior of a collection of interacting components. Dynamic contracts allow contract parameters to change at runtime and enable coordination of multiple interacting sub-systems.These results are demonstrated in the context of a freeway ramp meter and an adjacent arterial network

The Fifth NASA Symposium on VLSI Design

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design

Journal of Telecommunications and Information Technology, 2018, nr 1

kwartalni

Low Power Memory/Memristor Devices and Systems

This reprint focusses on achieving low-power computation using memristive devices. The topic was designed as a convenient reference point: it contains a mix of techniques starting from the fundamental manufacturing of memristive devices all the way to applications such as physically unclonable functions, and also covers perspectives on, e.g., in-memory computing, which is inextricably linked with emerging memory devices such as memristors. Finally, the reprint contains a few articles representing how other communities (from typical CMOS design to photonics) are fighting on their own fronts in the quest towards low-power computation, as a comparison with the memristor literature. We hope that readers will enjoy discovering the articles within