Model predictive control techniques for hybrid systems

This paper describes the main issues encountered when applying model predictive control to hybrid processes. Hybrid model predictive control (HMPC) is a research field non-fully developed with many open challenges. The paper describes some of the techniques proposed by the research community to overcome the main problems encountered. Issues related to the stability and the solution of the optimization problem are also discussed. The paper ends by describing the results of a benchmark exercise in which several HMPC schemes were applied to a solar air conditioning plant.Ministerio de Eduación y Ciencia DPI2007-66718-C04-01Ministerio de Eduación y Ciencia DPI2008-0581

Stochastic-Based Computing with Emerging Spin-Based Device Technologies

In this dissertation, analog and emerging device physics is explored to provide a technology platform to design new bio-inspired system and novel architecture. With CMOS approaching the nano-scaling, their physics limits in feature size. Therefore, their physical device characteristics will pose severe challenges to constructing robust digital circuitry. Unlike transistor defects due to fabrication imperfection, quantum-related switching uncertainties will seriously increase their susceptibility to noise, thus rendering the traditional thinking and logic design techniques inadequate. Therefore, the trend of current research objectives is to create a non-Boolean high-level computational model and map it directly to the unique operational properties of new, power efficient, nanoscale devices. The focus of this research is based on two-fold: 1) Investigation of the physical hysteresis switching behaviors of domain wall device. We analyze phenomenon of domain wall device and identify hysteresis behavior with current range. We proposed the Domain-Wall-Motion-based (DWM) NCL circuit that achieves approximately 30x and 8x improvements in energy efficiency and chip layout area, respectively, over its equivalent CMOS design, while maintaining similar delay performance for a one bit full adder. 2) Investigation of the physical stochastic switching behaviors of Mag- netic Tunnel Junction (MTJ) device. With analyzing of stochastic switching behaviors of MTJ, we proposed an innovative stochastic-based architecture for implementing artificial neural network (S-ANN) with both magnetic tunneling junction (MTJ) and domain wall motion (DWM) devices, which enables efficient computing at an ultra-low voltage. For a well-known pattern recognition task, our mixed-model HSPICE simulation results have shown that a 34-neuron S-ANN implementation, when compared with its deterministic-based ANN counterparts implemented with digital and analog CMOS circuits, achieves more than 1.5 ~ 2 orders of magnitude lower energy consumption and 2 ~ 2.5 orders of magnitude less hidden layer chip area

An extensive English language bibliography on graph theory and its applications

Bibliography on graph theory and its application

A guided tour of asynchronous cellular automata

Research on asynchronous cellular automata has received a great amount of attention these last years and has turned to a thriving field. We survey the recent research that has been carried out on this topic and present a wide state of the art where computing and modelling issues are both represented.Comment: To appear in the Journal of Cellular Automat

Kinetic approaches to lactose operon induction and bimodality

The quasi-equilibrium approximation is acceptable when molecular interactions are fast enough compared to circuit dynamics, but is no longer allowed when cellular activities are governed by rare events. A typical example is the lactose operon (lac), one of the most famous paradigms of transcription regulation, for which several theories still coexist to describe its behaviors. The lac system is generally analyzed by using equilibrium constants, contradicting single-event hypotheses long suggested by Novick and Weiner (1957). Enzyme induction as an all-or-none phenomenon. Proc. Natl. Acad. Sci. USA 43, 553-566) and recently refined in the study of (Choi et al., 2008. A stochastic single-molecule event triggers phenotype switching of a bacterial cell. Science 322, 442-446). In the present report, a lac repressor (LacI)-mediated DNA immunoprecipitation experiment reveals that the natural LacI-lac DNA complex built in vivo is extremely tight and long-lived compared to the time scale of lac expression dynamics, which could functionally disconnect the abortive expression bursts and forbid using the standard modes of lac bistability. As alternatives, purely kinetic mechanisms are examined for their capacity to restrict induction through: (i) widely scattered derepression related to the arrival time variance of a predominantly backward asymmetric random walk and (ii) an induction threshold arising in a single window of derepression without recourse to nonlinear multimeric binding and Hill functions. Considering the complete disengagement of the lac repressor from the lac promoter as the probabilistic consequence of a transient stepwise mechanism, is sufficient to explain the sigmoidal lac responses as functions of time and of inducer concentration. This sigmoidal shape can be misleadingly interpreted as a phenomenon of equilibrium cooperativity classically used to explain bistability, but which has been reported to be weak in this system

Dependency Stochastic Boolean Satisfiability: A Logical Formalism for NEXPTIME Decision Problems with Uncertainty

Stochastic Boolean Satisfiability (SSAT) is a logical formalism to model decision problems with uncertainty, such as Partially Observable Markov Decision Process (POMDP) for verification of probabilistic systems. SSAT, however, is limited by its descriptive power within the PSPACE complexity class. More complex problems, such as the NEXPTIME-complete Decentralized POMDP (Dec-POMDP), cannot be succinctly encoded with SSAT. To provide a logical formalism of such problems, we extend the Dependency Quantified Boolean Formula (DQBF), a representative problem in the NEXPTIME-complete class, to its stochastic variant, named Dependency SSAT (DSSAT), and show that DSSAT is also NEXPTIME-complete. We demonstrate the potential applications of DSSAT to circuit synthesis of probabilistic and approximate design. Furthermore, to study the descriptive power of DSSAT, we establish a polynomial-time reduction from Dec-POMDP to DSSAT. With the theoretical foundations paved in this work, we hope to encourage the development of DSSAT solvers for potential broad applications.Comment: 10 pages, 5 figures. A condensed version of this work is published in the AAAI Conference on Artificial Intelligence (AAAI) 202

Removing constant‐induced errors in stochastic circuits

Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/163790/1/cdt2bf00226.pd

Energy-Efficient FPGA-Based Parallel Quasi-Stochastic Computing

The high performance of FPGA (Field Programmable Gate Array) in image processing applications is justified by its flexible reconfigurability, its inherent parallel nature and the availability of a large amount of internal memories. Lately, the Stochastic Computing (SC) paradigm has been found to be significantly advantageous in certain application domains including image processing because of its lower hardware complexity and power consumption. However, its viability is deemed to be limited due to its serial bitstream processing and excessive run-time requirement for convergence. To address these issues, a novel approach is proposed in this work where an energy-efficient implementation of SC is accomplished by introducing fast-converging Quasi-Stochastic Number Generators (QSNGs) and parallel stochastic bitstream processing, which are well suited to leverage FPGA\u27s reconfigurability and abundant internal memory resources. The proposed approach has been tested on the Virtex-4 FPGA, and results have been compared with the serial and parallel implementations of conventional stochastic computation using the well-known SC edge detection and multiplication circuits. Results prove that by using this approach, execution time, as well as the power consumption are decreased by a factor of 3.5 and 4.5 for the edge detection circuit and multiplication circuit, respectively

Automated Synthesis of Memristor Crossbar Networks

The advancement of semiconductor device technology over the past decades has enabled the design of increasingly complex electrical and computational machines. Electronic design automation (EDA) has played a significant role in the design and implementation of transistor-based machines. However, as transistors move closer toward their physical limits, the speed-up provided by Moore\u27s law will grind to a halt. Once again, we find ourselves on the verge of a paradigm shift in the computational sciences as newer devices pave the way for novel approaches to computing. One of such devices is the memristor -- a resistor with non-volatile memory. Memristors can be used as junctional switches in crossbar circuits, which comprise of intersecting sets of vertical and horizontal nanowires. The major contribution of this dissertation lies in automating the design of such crossbar circuits -- doing a new kind of EDA for a new kind of computational machinery. In general, this dissertation attempts to answer the following questions: a. How can we synthesize crossbars for computing large Boolean formulas, up to 128-bit? b. How can we synthesize more compact crossbars for small Boolean formulas, up to 8-bit? c. For a given loop-free C program doing integer arithmetic, is it possible to synthesize an equivalent crossbar circuit? We have presented novel solutions to each of the above problems. Our new, proposed solutions resolve a number of significant bottlenecks in existing research, via the usage of innovative logic representation and artificial intelligence techniques. For large Boolean formulas (up to 128-bit), we have utilized Reduced Ordered Binary Decision Diagrams (ROBDDs) to automatically synthesize linearly growing crossbar circuits that compute them. This cutting edge approach towards flow-based computing has yielded state-of-the-art results. It is worth noting that this approach is scalable to n-bit Boolean formulas. We have made significant original contributions by leveraging artificial intelligence for automatic synthesis of compact crossbar circuits. This inventive method has been expanded to encompass crossbar networks with 1D1M (1-diode-1-memristor) switches, as well. The resultant circuits satisfy the tight constraints of the Feynman Grand Prize challenge and are able to perform 8-bit binary addition. A leading edge development for end-to-end computation with flow-based crossbars has been implemented, which involves methodical translation of loop-free C programs into crossbar circuits via automated synthesis. The original contributions described in this dissertation reflect the substantial progress we have made in the area of electronic design automation for synthesis of memristor crossbar networks