Exploiting pseudo-schedules to guide data dependence graph partitioning

This paper presents a new modulo scheduling algorithm for clustered microarchitectures. The main feature of the proposed scheme is that the assignment of instructions to clusters is done by means of graph partitioning algorithms that are guided by a pseudo-scheduler. This pseudo-scheduler is a simplified version of the full instruction scheduler and estimates key constraints that would be encountered in the final schedule. The final scheduling process is bi-directional and includes on-the-fly spill code generation. The proposed scheme is evaluated against previous scheduling approaches using the SPECfp95 benchmark suite. Our modeling results show that better schedules are obtained for most programs across a range of different architectures. For a 4-cluster VLIW architecture with 32 registers and a 2-cycle inter-cluster communication delay we obtain an average speedup of 38.5%.Peer ReviewedPostprint (published version

THE EFFECTIVENESS OF EDMODO TOWARDS INDONESIAN EFL LEARNERS’ ENGLISH PROFICIENCY

As a result of the utilization of technological advances to achieve competency integration, the 4.0 technology era is gaining traction in the field of education. This study aims to explore the efficacy of using the Edmodo application as an online-based learning medium in order to improve the way in which EFL students learn English using technology. By  a mixed-methods research design, this study recruited twenty-two tenth graders in the Mathematics and Natural Science stream from an integrated Islamic senior high school in Aceh province, Indonesia. The data indicate that the majority of students possess the necessary devices to assist them in completing their tasks, and a significant proportion of them use these devices to play games and conduct research. By categorizing aspects and components, Edmodo improves students' vocabulary when used to assess their learning progress through assignments and quizzes. In addition, the students are more willing to request assistance from teachers and peers when using the application. Despite the fact that Edmodo requires a smartphone and a reliable internet connection to utilize it, the participants do not report having any significant issues with the two requirements, however, half of them report having trouble attaching assignments from different types of files such as Doc, Pdf, Video, and Audio. Overall, Edmodo is an outstanding and highly effective online resource for reading, writing, listening, and speaking English classes (e-learning)

Addressing Academic and Faculty Challenges: Empowering Success and Accessibility with an Occupational Therapy Perspective

Introduction: The increasing presence of students with disabilities in higher education necessitates improved faculty support and awareness of on-campus support services and accommodations. Occupational therapists can play a vital role in promoting inclusion and Universal Design for Learning (UDL) principles by collaborating with faculty to enhance the academic experience and success of students with disabilities. Purpose: The primary aim of this project was to evaluate and educate faculty on student support services at the University and share knowledge on Universal Design for Learning to enhance the existing literature on the significance of OT in higher education. Approach: I completed an extensive literature search, needs assessments, and conducted various semi-structured interviews with professionals at St. Catherine University. A faculty resource survey was created to gather information from faculty on support resources that would benefit the campus community. Outcomes: Overall, the faculty showed positive attitudes towards Universal Design for Learning (UDL) as the top priority. Common themes identified from the faculty resource survey were knowledge of accessibility, communication, knowledge of student resources and faculty resources, staffing, and ease of locating resources. Recommendations: The Student Accessibility and Accommodations (SA&A) office and the occupational therapy profession can continue collaborating to support faculty, staff, and students. A future capstone student could create a UDL program for faculty and evaluate faculty resources

Soft-error resilient on-chip memory structures

Soft errors induced by energetic particle strikes in on-chip memory structures, such as L1 data/instruction caches and register files, have become an increasing challenge in designing new generation reliable microprocessors. Due to their transient/random nature, soft errors cannot be captured by traditional verification and testing process due to the irrelevancy to the correctness of the logic. This dissertation is thus focusing on the reliability characterization and cost-effective reliable design of on-chip memories against soft errors. Due to various performance, area/size, and energy constraints in various target systems, many existing unoptimized protection schemes on cache memories may eventually prove significantly inadequate and ineffective. This work develops new lifetime models for data and tag arrays residing in both the data and instruction caches. These models facilitate the characterization of cache vulnerability of the stored items at various lifetime phases. The design methodology is further exemplified by the proposed reliability schemes targeting at specific vulnerable phases. Benchmarking is carried out to showcase the effectiveness of these approaches. The tag array demands high reliability against soft errors while the data array is fully protected in on-chip caches, because of its crucial importance to the correctness of cache accesses. Exploiting the address locality of memory accesses, this work proposes a Tag Replication Buffer (TRB) to protect information integrity of the tag array in the data cache with low performance, energy and area overheads. To provide a comprehensive evaluation of the tag array reliability, this work also proposes a refined evaluation metric, detected-without-replica-TVF (DOR-TVF), which combines the TVF and access-with-replica (AWR) analysis. Based on the DOR-TVF analysis, a TRB scheme with early write-back (TRB-EWB) is proposed, which achieves a zero DOR-TVF at a negligible performance overhead. Recent research, as well as the proposed optimization schemes in this cache vulnerability study, have focused on the design of cost-effective reliable data caches in terms of performance, energy, and area overheads based on the assumption of fixed error rates. However, for systems in operating environments that vary with time or location, those schemes will be either insufficient or over-designed for the changing error rates. This work explores the design of a self-adaptive reliable data cache that dynamically adapts its employed reliability schemes to the changing operating environments in order to maintain a target reliability. The experimental evaluation shows that the self-adaptive data cache achieves similar reliability to a cache protected by the most reliable scheme, while simultaneously minimizing the performance and power overheads. Besides the data/instruction caches, protecting the register file and its data buses is crucial to reliable computing in high-performance microprocessors. Since the register file is in the critical path of the processor pipeline, any reliable design that increases either the pressure on the register file or the register file access latency is not desirable. This work proposes to exploit narrow-width register values, which represent the majority of generated values, for making the duplicates within the same register data item. A detailed architectural vulnerability factor (AVF) analysis shows that this in-register duplication (IRD) scheme significantly reduces the AVF in the register file compared to the conventional design. The experimental evaluation also shows that IRD provides superior read-with-duplicate (RWD) and error detection/recovery rates under heavy error injection as compared to previous reliability schemes, while only incurring a small power overhead. By integrating the proposed reliable designs in data/instruction caches and register files, the vulnerability of the entire microprocessor is dramatically reduced. The new lifetime model, the self-adaptive design and the narrow-width value duplication scheme proposed in this work can also provide guidance to architects toward highly efficient reliable system design

The effectiveness of teamwork training on teamwork behaviors and team performance : A systematic review and meta-analysis of controlled interventions

The objective of this study was to conduct a systematic review and meta-analysis of teamwork interventions that were carried out with the purpose of improving teamwork and team performance, using controlled experimental designs. A literature search returned 16,849 unique articles. The meta-analysis was ultimately conducted on 51 articles, comprising 72 (k) unique interventions, 194 effect sizes, and 8439 participants, using a random effects model. Positive and significant medium-sized effects were found for teamwork interventions on both teamwork and team performance. Moderator analyses were also conducted, which generally revealed positive and significant effects with respect to several sample, intervention, and measurement characteristics. Implications for effective teamwork interventions as well as considerations for future research are discussed

DASICS: Enhancing Memory Protection with Dynamic Compartmentalization

In the existing software development ecosystem, security issues introduced by third-party code cannot be overlooked. Among these security concerns, memory access vulnerabilities stand out prominently, leading to risks such as the theft or tampering of sensitive data. To address this issue, software-based defense mechanisms have been established at the programming language, compiler, and operating system levels. However, as a trade-off, these mechanisms significantly reduce software execution efficiency. Hardware-software co-design approaches have sought to either construct entirely isolated trusted execution environments or attempt to partition security domains within the same address space. While such approaches enhance efficiency compared to pure software methods, they also encounter challenges related to granularity of protection, performance overhead, and portability. In response to these challenges, we present the DASICS (Dynamic in-Address-Space Isolation by Code Segments) secure processor design, which offers dynamic and flexible security protection across multiple privilege levels, addressing data flow protection, control flow protection, and secure system calls. We have implemented hardware FPGA prototypes and software QEMU simulator prototypes based on DASICS, along with necessary modifications to system software for adaptability. We illustrate the protective mechanisms and effectiveness of DASICS with two practical examples and provide potential real-world use cases where DASICS could be applied.Comment: 16 pages, 6 figure

Creating a content management system to support K-12 teachers implementing a web enhanced classroom

Using instructional design methodology, this project identified the features of an effective classroom website and incorporated them into the design of a Course Management System (CMS) for K-12 teachers. The purpose of this CMS is to deliver online information to students and parents while meeting the needs of K-12 teachers