5,228 research outputs found
An efficient logic fault diagnosis framework based on effect-cause approach
Fault diagnosis plays an important role in improving the circuit design process and the
manufacturing yield. With the increasing number of gates in modern circuits, determining
the source of failure in a defective circuit is becoming more and more challenging.
In this research, we present an efficient effect-cause diagnosis framework for
combinational VLSI circuits. The framework consists of three stages to obtain an accurate
and reasonably precise diagnosis. First, an improved critical path tracing algorithm is
proposed to identify an initial suspect list by backtracing from faulty primary outputs
toward primary inputs. Compared to the traditional critical path tracing approach, our
algorithm is faster and exact. Second, a novel probabilistic ranking model is applied to
rank the suspects so that the most suspicious one will be ranked at or near the top. Several
fast filtering methods are used to prune unrelated suspects. Finally, to refine the diagnosis,
fault simulation is performed on the top suspect nets using several common fault models.
The difference between the observed faulty behavior and the simulated behavior is used to rank each suspect. Experimental results on ISCAS85 benchmark circuits show that this
diagnosis approach is efficient both in terms of memory space and CPU time and the
diagnosis results are accurate and reasonably precise
Health Condition Monitoring and Fault-Tolerant Operation of Adjustable Speed Drives
Adjustable speed drives (ASDs) have been extensively used in industrial applications over the past few decades because of their benefits of energy saving and control flexibilities. However, the wider penetration of ASD systems into industrial applications is hindered by the lack of health monitoring and fault-tolerant operation techniques, especially in safety-critical applications. In this dissertation, a comprehensive portfolio of health condition monitoring and fault-tolerant operation strategies is developed and implemented for multilevel neutral-point-clamped (NPC) power converters in ASDs. Simulations and experiments show that these techniques can improve power cycling lifetime of power transistors, on-line diagnosis of switch faults, and fault-tolerant capabilities.The first contribution of this dissertation is the development of a lifetime improvement Pulse Width Modulation (PWM) method which can significantly extend the power cycling lifetime of Insulated Gate Bipolar Transistors (IGBTs) in NPC inverters operating at low frequencies. This PWM method is achieved by injecting a zero-sequence signal with a frequency higher than that of the IGBT junction-to-case thermal time constants. This, in turn, lowers IGBT junction temperatures at low output frequencies. Thermal models, simulation and experimental verifications are carried out to confirm the effectiveness of this PWM method. As a second contribution of this dissertation, a novel on-line diagnostic method is developed for electronic switch faults in power converters. Targeted at three-level NPC converters, this diagnostic method can diagnose any IGBT faults by utilizing the information on the dc-bus neutral-point current and switching states. This diagnostic method only requires one additional current sensor for sensing the neutral-point current. Simulation and experimental results verified the efficacy of this diagnostic method.The third contribution consists of the development and implementation of a fault-tolerant topology for T-Type NPC power converters. In this fault-tolerant topology, one additional phase leg is added to the original T-Type NPC converter. In addition to providing a fault-tolerant solution to certain switch faults in the converter, this fault-tolerant topology can share the overload current with the original phase legs, thus increasing the overload capabilities of the power converters. A lab-scale 30-kVA ASD based on this proposed topology is implemented and the experimental results verified its benefits
AI/ML Algorithms and Applications in VLSI Design and Technology
An evident challenge ahead for the integrated circuit (IC) industry in the
nanometer regime is the investigation and development of methods that can
reduce the design complexity ensuing from growing process variations and
curtail the turnaround time of chip manufacturing. Conventional methodologies
employed for such tasks are largely manual; thus, time-consuming and
resource-intensive. In contrast, the unique learning strategies of artificial
intelligence (AI) provide numerous exciting automated approaches for handling
complex and data-intensive tasks in very-large-scale integration (VLSI) design
and testing. Employing AI and machine learning (ML) algorithms in VLSI design
and manufacturing reduces the time and effort for understanding and processing
the data within and across different abstraction levels via automated learning
algorithms. It, in turn, improves the IC yield and reduces the manufacturing
turnaround time. This paper thoroughly reviews the AI/ML automated approaches
introduced in the past towards VLSI design and manufacturing. Moreover, we
discuss the scope of AI/ML applications in the future at various abstraction
levels to revolutionize the field of VLSI design, aiming for high-speed, highly
intelligent, and efficient implementations
Fault Management in DC Microgrids:A Review of Challenges, Countermeasures, and Future Research Trends
The significant benefits of DC microgrids have instigated extensive efforts to be an alternative network as compared to conventional AC power networks. Although their deployment is ever-growing, multiple challenges still occurred for the protection of DC microgrids to efficiently design, control, and operate the system for the islanded mode and grid-tied mode. Therefore, there are extensive research activities underway to tackle these issues. The challenge arises from the sudden exponential increase in DC fault current, which must be extinguished in the absence of the naturally occurring zero crossings, potentially leading to sustained arcs. This paper presents cut-age and state-of-the-art issues concerning the fault management of DC microgrids. It provides an account of research in areas related to fault management of DC microgrids, including fault detection, location, identification, isolation, and reconfiguration. In each area, a comprehensive review has been carried out to identify the fault management of DC microgrids. Finally, future trends and challenges regarding fault management in DC-microgrids are also discussed
Autonomous Systems, Robotics, and Computing Systems Capability Roadmap: NRC Dialogue
Contents include the following: Introduction. Process, Mission Drivers, Deliverables, and Interfaces. Autonomy. Crew-Centered and Remote Operations. Integrated Systems Health Management. Autonomous Vehicle Control. Autonomous Process Control. Robotics. Robotics for Solar System Exploration. Robotics for Lunar and Planetary Habitation. Robotics for In-Space Operations. Computing Systems. Conclusion
NASA space station automation: AI-based technology review
Research and Development projects in automation for the Space Station are discussed. Artificial Intelligence (AI) based automation technologies are planned to enhance crew safety through reduced need for EVA, increase crew productivity through the reduction of routine operations, increase space station autonomy, and augment space station capability through the use of teleoperation and robotics. AI technology will also be developed for the servicing of satellites at the Space Station, system monitoring and diagnosis, space manufacturing, and the assembly of large space structures
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