Performance enhancement in the desing of amplifier and amplifier-less circuits in modern CMOS technologies.

In the context of nowadays CMOS technology downscaling and the increasing demand of high performance electronics by industry and consumers, analog design has become a major challenge. On the one hand, beyond others, amplifiers have traditionally been a key cell for many analog systems whose overall performance strongly depends on those of the amplifier. Consequently, still today, achieving high performance amplifiers is essential. On the other hand, due to the increasing difficulty in achieving high performance amplifiers in downscaled modern technologies, a different research line that replaces the amplifier by other more easily achievable cells appears: the so called amplifier-less techniques. This thesis explores and contributes to both philosophies. Specifically, a lowvoltage differential input pair is proposed, with which three multistage amplifiers in the state of art are designed, analysed and tested. Moreover, a structure for the implementation of differential switched capacitor circuits, specially suitable for comparator-based circuits, that features lower distortion and less noise than the classical differential structures is proposed, an, as a proof of concept, implemented in a ΔΣ modulator

CMOS current amplifiers : speed versus nonlinearity

This work deals with analogue integrated circuit design using various types of current-mode amplifiers. These circuits are analysed and realised using modern CMOS integration technologies. The dynamic nonlinearities of these circuits are discussed in detail as in the literature only linear nonidealities and static nonlinearities are conventionally considered. For the most important open-loop current-mode amplifier, the second-generation current-conveyor (CCII), a macromodel is derived that, unlike other reported macromodels, can accurately predict the common-mode behaviour in differential applications. Similarly, this model is used to describe the nonidealities of several other current-mode amplifiers because similar circuit structures are common in such amplifiers. With modern low-voltage CMOS-technologies, the current-mode operational amplifier and the high-gain current-conveyor (CCII∞) perform better than open-loop current-amplifiers. Similarly, unlike with conventional voltage-mode operational amplifiers, the large-signal settling behaviour of these two amplifier types does not degrade as CMOS-processes are scaled down. In this work, two 1 MHz 3rd -order low-pass continuous-time filters are realised with a 1.2 μm CMOS-process. These filters use a differential CCII∞ with linearised, dynamically biased output stages resulting in performance superior to most OTA-C filter realisations reported. Similarly, two logarithmic amplifier chips are designed and fabricated. The first circuit, implemented with a 1.2 μm BiCMOS-process, uses again a CCII∞. This circuit uses a pn-junction as a logarithmic feedback element. With a CCII∞ the constant gain-bandwidth product, typical of voltage-mode operational amplifiers, is avoided resulting in a constant 1 MHz bandwidth with a 60 dB signal amplitude range. The second current-mode logarithmic amplifier, based on piece-wise linear approximation of the logarithmic function by a cascade of limiting current amplifier stages, is realised in a standard 1.2 μm CMOS-process. The limiting level in these current amplifiers is less sensitive to process variation than in limiting voltage amplifiers resulting in exceptionally low temperature dependency of the logarithmic output signal. Additionally, along with this logarithmic amplifier a new current peak detectoris developed.reviewe

Frequency compensation of CMOS operational amplifier.

Ho Kin-Pui.Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.Includes bibliographical references (leaves 92-95).Abstracts in English and Chinese.Abstract --- p.2摘要 --- p.4Acknowledgements --- p.5Table of Contents --- p.6List of Figures --- p.10List of Tables --- p.14Chapter Chapter 1 --- Introduction --- p.15Overview --- p.15Objective --- p.17Thesis Organization --- p.17Chapter Chapter 2 --- Fundamentals of Operational Amplifier --- p.19Chapter 2.1 --- Definitions of Commonly Used Figures --- p.19Chapter 2.1.1 --- Input Differential Voltage Range --- p.19Chapter 2.1.2 --- Maximum Output Voltage Swing --- p.20Chapter 2.1.3 --- Input Common Mode Voltage Range --- p.20Chapter 2.1.4 --- Input Offset Voltage --- p.20Chapter 2.1.5 --- Gain Bandwidth Product --- p.21Chapter 2.1.6 --- Phase Margin --- p.22Chapter 2.1.7 --- Slew Rate --- p.22Chapter 2.1.8 --- Settling Time --- p.23Chapter 2.1.9 --- Common Mode Rejection Ratio --- p.23Chapter 2.2 --- Frequency Compensation of Operational Amplifier --- p.24Chapter 2.2.1 --- Overview --- p.24Chapter 2.2.2 --- Miller Compensation --- p.25Chapter Chapter 3 --- CMOS Current Feedback Operational Amplifier --- p.27Chapter 3.1 --- Introduction --- p.27Chapter 3.2 --- Current Feedback Operational Amplifier with Active Current Mode Compensation --- p.28Chapter 3.2.1 --- Circuit Description --- p.29Chapter 3.2.2 --- Small Signal analysis --- p.32Chapter 3.2.3 --- Simulation Results --- p.34Chapter Chapter 4 --- Reversed Nested Miller Compensation --- p.38Chapter 4.1 --- Introduction --- p.38Chapter 4.2 --- Frequency Response --- p.39Chapter 4.2.1 --- Gain-bandwidth product --- p.40Chapter 4.2.2 --- Right half complex plane zero --- p.40Chapter 4.2.3 --- The Pair of Complex Conjugate Poles --- p.42Chapter 4.3 --- Components Sizing --- p.47Chapter 4.4 --- Circuit Simulation --- p.48Chapter Chapter 5 --- Enhancement Technique for Reversed Nested Miller Compensation --- p.54Chapter 5.1 --- Introduction --- p.54Chapter 5.2 --- Working principle of the proposed circuit --- p.54Chapter 5.2.1 --- The introduction of nulling resistor --- p.55Chapter 5.2.2 --- The introduction of a voltage buffer --- p.55Chapter 5.2.3 --- Small Signal Analysis --- p.57Chapter 5.2.4 --- Sign Inversion of the RHP Zero with Nulling Resistor --- p.59Chapter 5.2.5 --- Frequency Multiplication of the Complex Conjugate Poles --- p.60Chapter 5.2.6 --- Stability Conditions --- p.63Chapter 5.3 --- Performance Comparison --- p.67Chapter 5.4 --- Conclusion: --- p.70Chapter 5.4.1 --- Circuit Modifications: --- p.70Chapter 5.4.2 --- Advantages: --- p.71Chapter Chapter 6 --- Physical Design of Operational Amplifier --- p.72Chapter 6.1 --- Introduction --- p.72Chapter 6.2 --- Transistor Layout Techniques --- p.72Chapter 6.2.1 --- Multi-finger Layout Technique --- p.72Chapter 6.2.2 --- Common-Centroid Structure --- p.73Chapter 6.3 --- Layout Techniques of Passive Components --- p.74Chapter 6.3.1 --- Capacitor Layout --- p.74Chapter 6.3.2 --- Resistor Layout --- p.75Chapter Chapter 7 --- Measurement Results --- p.77Chapter 7.1 --- Overview --- p.77Chapter 7.2 --- Measurement Results for the Current Feedback Operational Amplifier --- p.77Chapter 7.2.1 --- Frequency Response of the inverting amplifier --- p.77Chapter 7.3 --- Measurement Results for the Three-Stage Operational Amplifier --- p.80Chapter 7.3.1 --- Input Offset Voltage Measurement --- p.80Chapter 7.3.2 --- Input Common Mode Range Measurement --- p.80Chapter 7.3.3 --- Gain Band width Measurement --- p.81Chapter 7.3.4 --- DC Gain measurement --- p.85Chapter 7.3.5 --- Slew Rate Measurement --- p.87Chapter 7.3.6 --- Phase Margin --- p.88Chapter 7.3.7 --- Performance Summary --- p.89Chapter Chapter 8 --- Conclusions --- p.90Chapter Chapter 9 --- Appendix --- p.9

The design of active resistors and transductors in a CMOS technology

Merged with duplicate record 10026.1/2618 on 07.20.2017 by CS (TIS)This thesis surveys linearisation techniques for implementing monolithic MOS active resistors and transconductors, and investigates the design of linear tunable resistors and transconductors. Improving linearity and tunability in the presence of non-ideal factors such as bulk modulation, mobility-degradation effects and mismatch of transistors is a principal objective. A family of new non-saturation-mode resistors and two novel saturation-mode transconductors are developed. Where possible, approximate analytical expressions are derived to explain the principles of operation. Performance comparisons of the new structures are made with other well-known circuits and their relative advantages and disadvantages evaluated. Experimental and simulation results are presented which validate the proposed linearisation techniques. It is shown that the proposed family of resistors offers improved linearity whilst the transconductors combine extended tunability with low distortion. Continuous-time filter examples are given to demonstrate the potential of these circuits for application in analogue signal-processing tasks.GEC Plessey Semiconductors, Plymout

Design of a low-noise optoelectronic amplifier channel for a laser radar

Abstract. The goal of this Master’s thesis is to find and develop the best topologies and circuit structures for a low-noise amplifier channel for a laser radar application. In this work different topologies, their strengths, weaknesses and challenges are studied. Low-noise optoelectronic amplifier channels have been used extensively in a variety of applications such as wireless communication, optical receivers and laser radar. The common constraint for all the mentioned applications is the noise. The optical input signal for optoelectronic receivers can be very weak. In order to detect the signal reliably and accurately, the receiver must not add significant noise to the input signal. Therefore, this thesis concentrates on improving the signal to noise ratio (SNR) by minimizing the noise sources, filtering the high frequency noise and amplifying the signal. In addition, the delay of the whole channel should be constant with respect to signal strength, supply voltage etc. variations. This low-noise optoelectronic amplifier channel can be employed in a laser radar to detect the distance of several kilometers.Pienikohinaisen optoelektronisen vahvistinkanavan suunnittelu lasertutkasovellukseen. Tiivistelmä. Tämän diplomityön tavoitteena on etsiä ja kehittää sopivia piiriratkaisuja ja -rakenteita lasertutkan pienikohinaiseen vahvistinkanavaan. Työssä tutkittiin eri rakenteita, niiden vahvuuksia, heikkouksia ja haasteita. Pienikohinaisia optoelektronisia vahvistinkanavia on käytetty paljon useissa sovelluksissa kuten langattomassa viestinnässä, optisissa vastaanottimissa ja lasertutkissa. Näissä sovelluksissa yhteisenä haasteena on kohina. Optoelektronisen vastaanottimen tulosignaali voi olla hyvin heikko, joten tarkan ja luotettavan vastaanoton varmistamiseksi vastaanottimen itsessään tulee olla hyvin pienikohinainen. Tässä työssä keskityttiinkin signaalikohinasuhteen (SNR) optimointiin minimoimalla itse kohinalähteet, suodattamalla korkeataajuista kohinaa ja vahvistamalla signaalia. Lisäksi koko kanavan viive oli pidettävä mahdollisimman vakiona eri signaalitasoilla, eri lämpötiloissa, eri käyttöjännitteillä jne. Työssä kehitettyä optoelektronista vahvistinkanavaa voidaan käyttää lasertutkissa mittaamaan etäisyyksiä kilometrien päässä oleviin kohteisiin

Super-gain-boosted AB-AB fully differential Miller op-amp with 156dB open-loop gain and 174MV/V MHZ pF/uW figure of merit in 130nm CMOS technology

A fully differential Miller op-amp with a composite input stage using resistive local common-mode feedback and regulated cascode transistors is presented here. High gain pseudo-differential auxiliary amplifiers are used to implement the regulated cascode transistors in order to boost the output impedance of the composite input stage and the open-loop gain of the op-amp. Both input and output stages operate in class AB mode. The proposed op-amp has been simulated in a 130nm commercial CMOS process technology. It operates from a 1.2V supply and has a close to rail-to-rail differential output swing. It has 156dB DC open-loop gain and 63MHz gain-bandwidth product with a 30pF capacitive load. The op-amp has a DC open-loop gain figure of merit FOMAOLDC of 174 (MV/V) MHz pF/uW and large-signal figure of merit FOMLS of 3(V/us) pF/uW.This work was supported in part by the Spanish Government Agencia Estatal de Investigación (AEI) under Grant TEC2016-80396-C2, in part by the Consejería de Economía y Conocimiento of Junta de Andalucía under Grant P18-FR-4317 (both projects received support from the Fondo Europeo de Desarrollo Regional (FEDER)), and in part by the Consejo Nacional de Ciencia y Tecnologia (CONACyT) under Grant A1-S-43214