108 research outputs found
CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit
This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS technology. Starting from a review of available CMOS circuit primitives and their respective merits and drawbacks, the paper proposes a synthesis approach for PWL dynamic systems, based on state-variable methods, and identifies the associated analog operators. The GmC approach, combining quasi-linear VCCS's, PWL VCCS's, and capacitors is then explored regarding the implementation of these operators. CMOS basic building blocks for the realization of the quasi-linear VCCS's and PWL VCCS's are presented and applied to design a Chua's circuit IC. The influence of GmC parasitics on the performance of dynamic PWL systems is illustrated through this example. Measured chaotic attractors from a Chua's circuit prototype are given. The prototype has been fabricated in a 2.4- mu m double-poly n-well CMOS technology, and occupies 0.35 mm/sup 2/, with a power consumption of 1.6 mW for a +or-2.5-V symmetric supply. Measurements show bifurcation toward a double-scroll Chua's attractor by changing a bias current
Robust symmetric multiplication for programmable analog VLSI array processing
This paper presents an electrically programmable analog multiplier. The circuit performs the multiplication between an input variable and an electrically selectable scaling factor. The multiplier is divided in several blocks: a linearized transconductor, binary weighted current mirrors and a differential to single-ended current adder. This paper shows the advantages introduced using a linearized OTA-based multiplier. The circuit presented renders higher linearity and symmetry in the output current than a previously reported single-transistor multiplier. Its inclusion in an array processor based on CNN allows for a more accurate implementation of the processing model and a more robust weight distribution scheme than those found in previous designs.Office of Naval Research (USA) N-00014- 02-1-0884Ministerio de Ciencia y Tecnología TIC2003-09817-C02-0
A wide dynamic range high-q high-frequency bandpass filter with an automatic quality factor tuning scheme
An 80 MHz bandpass filter with a tunable quality factor of 16∼44 using an improved transconductor circuit is presented. A noise optimized biquad structure for high-Q, high- frequency bandpass filter is proposed. The quality factor of the filter is tuned using a new quality factor locked loop algorithm. It was shown that a second-order quality factor locked loop is necessary and sufficient to tune the quality factor of a bandpass filter with zero steady state error. The accuracy, mismatch, and sensitivty analysis of the new tuning scheme was performed and analyzed. Based on the proposed noise optimized filter structure and new quality factor tuning scheme, a biquad filter was designed and fabricated in 0.25 μm BiCMOS process. The measured results show that the biquad filter achieves a SNR of 45 dB at IMD of 40 dB. The P-1dB compression point and IIP3 of the filter are -10 dBm and -2.68 dBm, respectively. The proposed biquad filter and quality factor tuning scheme consumes 58mW and 13 mW of power at 3.3 V supply.Ph.D.Committee Chair: Allen Phillip; Committee Member: Hasler Paul; Committee Member: Keezer David; Committee Member: Kenny James; Committee Member: Pan Ronghu
Analysis and design of wideband voltage controlled oscillators using self-oscillating active inductors.
Voltage controlled oscillators (VCOs) are essential components of RF circuits used in
transmitters and receivers as sources of carrier waves with variable frequencies. This, together
with a rapid development of microelectronic circuits, led to an extensive research
on integrated implementations of the oscillator circuits. One of the known approaches
to oscillator design employs resonators with active inductors electronic circuits simulating
the behavior of passive inductors using only transistors and capacitors. Such
resonators occupy only a fraction of the silicon area necessary for a passive inductor,
and thus allow to use chip area more eectively. The downsides of the active inductor
approach include: power consumption and noise introduced by transistors.
This thesis presents a new approach to active inductor oscillator design using selfoscillating
active inductor circuits. The instability necessary to start oscillations is
provided by the use of a passive RC network rather than a power consuming external
circuit employed in the standard oscillator approach. As a result, total power consumption
of the oscillator is improved. Although, some of the active inductors with
RC circuits has been reported in the literature, there has been no attempt to utilise
this technique in wideband voltage controlled oscillator design. For this reason, the
dissertation presents a thorough investigation of self-oscillating active inductor circuits,
providing a new set of design rules and related trade-os. This includes: a complete
small signal model of the oscillator, sensitivity analysis, large signal behavior of the circuit
and phase noise model. The presented theory is conrmed by extensive simulations
of wideband CMOS VCO circuit for various temperatures and process variations. The obtained results prove that active inductor oscillator performance is obtained without
the use of standard active compensation circuits. Finally, the concept of self-oscillating
active inductor has been employed to simple and fast OOK (On-Off Keying) transmitter
showing energy eciency comparable to the state of the art implementations reported
in the literature
A Low-Voltage CMOS Buffer for RF Applications Based on a Fully-Differential Voltage-Combiner
Part 20: Electronics: RF ApplicationsInternational audienceThis paper presents a new CMOS buffer circuit topology for radio-frequency (RF) applications based on a fully-differential voltage-combiner circuit, capable of operating at low-voltage. The proposed circuit uses a combination of common-source (CS) and common-drain (CD) devices. The simulation results show good levels of linearity and bandwidth. To improve total harmonic distortion (THD) a source degeneration technique is used. The proposed circuit has been designed in a 130nm logic CMOS technology and it achieves a simulated gain of 1.54 dB, a bandwidth of 1.14 GHz for a total power dissipation of 13.34 mW, when driving an RF active probe (with 0.8 pF in parallel with 200 kΩ)
The design of active resistors and transductors in a CMOS technology
Merged with duplicate record 10026.1/2618 on 07.20.2017 by CS (TIS)This thesis surveys linearisation techniques for implementing monolithic MOS
active resistors and transconductors, and investigates the design of linear tunable
resistors and transconductors. Improving linearity and tunability in the presence
of non-ideal factors such as bulk modulation, mobility-degradation effects and mismatch
of transistors is a principal objective. A family of new non-saturation-mode
resistors and two novel saturation-mode transconductors are developed. Where
possible, approximate analytical expressions are derived to explain the principles
of operation. Performance comparisons of the new structures are made with other
well-known circuits and their relative advantages and disadvantages evaluated.
Experimental and simulation results are presented which validate the proposed
linearisation techniques. It is shown that the proposed family of resistors offers
improved linearity whilst the transconductors combine extended tunability with
low distortion. Continuous-time filter examples are given to demonstrate the
potential of these circuits for application in analogue signal-processing tasks.GEC Plessey Semiconductors, Plymout
An asymmetrical bulk-modified composite MOS transistor with enhanced linearity
In this work, an asymmetrical bulk-linearized composite MOSFET is presented, with an enhanced linear range and an equivalent saturation voltage of up to several hundred mV
even in weak inversion, allowing to implement large MOS resistors. Some preliminary measurements are presented, as well as 150MΩ and 200MΩ equivalent resistors simulations, with a linear range up to 1.5V. A low frequency, 40dB gain, fully integrated cardiac sensing channel filter/amplifier is also shown. Taking advantage of the proposed technique, the circuit consumes only 25nA of supply current.Agencia Nacional de Investigación e Innovació
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