CMOS power amplifier and transmitter front-end design in wireless communication.

Ng, Yuen Sum.Thesis (M.Phil.)--Chinese University of Hong Kong, 2009.Includes bibliographical references.Abstract also in Chinese.Chapter 1. --- INTRODUCTION --- p.11Chapter 1.1 --- Motivation --- p.11Chapter 1.2 --- Specifications --- p.12Chapter 1.3 --- Organization of the Thesis --- p.16Chapter 1.4 --- References --- p.16Chapter 2. --- BASIC THEORY OF POWER AMPLIFIER AND TRANSMITTER FRONT-END --- p.18Chapter 2.1 --- Classification of Power Amplifier --- p.18Chapter 2.1.1 --- Class A --- p.20Chapter 2.1.2 --- Class B --- p.21Chapter 2.1.3 --- Class AB --- p.22Chapter 2.1.4 --- Class C --- p.23Chapter 2.1.5 --- Class D --- p.24Chapter 2.1.6 --- Class E --- p.25Chapter 2.1.7 --- Class F --- p.28Chapter 2.2 --- Figure-of-Mhrit of Power Amplifier --- p.28Chapter 2.2.1 --- Small Signal Analysis --- p.29Chapter 2.2.1.1 --- S-parameter --- p.29Chapter 2.2.1.2 --- Gain and Stability --- p.29Chapter 2.2.2 --- Large Signal Analysis --- p.32Chapter 2.2.2.1 --- 1-dB compression point --- p.33Chapter 2.2.2.2 --- Third-order intermodulation point --- p.33Chapter 2.2.2.3 --- Power Gain --- p.35Chapter 2.2.2.4 --- Drain Efficiency and Power Added Efficiency --- p.35Chapter 2.2.2.5 --- AM-AM and AM-PM conversion --- p.36Chapter 2.2.3 --- Modulation Analysis --- p.36Chapter 2.2.3.1 --- Constellation Diagram and Error Vector Magnitude --- p.36Chapter 2.3 --- Reference --- p.37Chapter 3. --- CIRCUIT DESIGN OF POWER AMPLIFIER --- p.39Chapter 3.1 --- Introduction --- p.39Chapter 3.2 --- Topology of the Power Amplifier Design --- p.39Chapter 3.3 --- Design in Power Amplifier --- p.40Chapter 3.2.1 --- Power Stage --- p.40Chapter 3.2.2 --- Driver Stage and Input matching --- p.46Chapter 3.4 --- Simulation Result on Power Amplifier --- p.49Chapter 3.5 --- Layout consideration --- p.50Chapter 3.6 --- Measurement Result on Power Amplifier --- p.51Chapter 3.4.1 --- Small signal measurement --- p.52Chapter 3.4.2 --- Large signal measurement --- p.55Chapter 3.4.3 --- Modulation measurement --- p.56Chapter 3.7 --- Performance Summary --- p.58Chapter 3.8 --- Reference --- p.59Chapter 4. --- CIRCUIT DESIGN OF TRANSMITTER FRONT-END --- p.60Chapter 4.1 --- Introduction --- p.60Chapter 4.2 --- Topology of the Transmitter Front-End Design --- p.61Chapter 4.3 --- Design in transmitter front-end circuit --- p.64Chapter 4.2.1 --- I/Q Modulator --- p.64Chapter 4.2.2 --- Power Amplifier --- p.66Chapter 4.2.3 --- On-chip LC Balun --- p.72Chapter 4.4 --- Simulation Result of the Transmitter Front-End Design --- p.74Chapter 4.5 --- Layout consideration --- p.75Chapter 4.6 --- Measurement Result of the Transmitter Front-End Design --- p.76Chapter 4.4.1. --- Transmitter Front-End Measurement --- p.77Chapter 4.4.1.1 --- Output Reflection coefficient --- p.77Chapter 4.4.1.2 --- Large Signal Measurement --- p.78Chapter 4.4.1.3 --- Modulation Measurement --- p.81Chapter 4.4.2. --- LC Balun Measurement --- p.84Chapter 4.7 --- Performance Summary of the transmitter front-end circuit --- p.86Chapter 4.8 --- Reference --- p.89Chapter 5. --- CONCLUSION --- p.90Chapter 6. --- FUTURE WORK --- p.9

A digital polar transmitter for multi-band OFDM Ultra-WideBand

Linear power amplifiers used to implement the Ultra-Wideband standard must be backed off from optimum power efficiency to meet the standard specifications and the power efficiency suffers. The problem of low efficiency can be mitigated by polar modulation. Digital polar architectures have been employed on numerous wireless standards like GSM, EDGE, and WLAN, where the fractional bandwidths achieved are only about 1%, and the power levels achieved are often in the vicinity of 20 dBm. Can the architecture be employed on wireless standards with low-power and high fractional bandwidth requirements and yet achieve good power efficiency? To answer these question, this thesis studies the application of a digital polar transmitter architecture with parallel amplifier stages for UWB. The concept of the digital transmitter is motivated and inspired by three factors. First, unrelenting advances in the CMOS technology in deep-submicron process and the prevalence of low-cost Digital Signal processing have resulted in the realization of higher level of integration using digitally intensive approaches. Furthermore, the architecture is an evolution of polar modulation, which is known for high power efficiency in other wireless applications. Finally, the architecture is operated as a digital-to-analog converter which circumvents the use of converters in conventional transmitters. Modeling and simulation of the system architecture is performed on the Agilent Advanced Design System Ptolemy simulation platform. First, by studying the envelope signal, we found that envelope clipping results in a reduction in the peak-to-average power ratio which in turn improves the error vector magnitude performance (figure of merit for the study). In addition, we have demonstrated that a resolution of three bits suffices for the digital polar transmitter when envelope clipping is performed. Next, this thesis covers a theoretical derivation for the estimate of the error vector magnitude based on the resolution, quantization and phase noise errors. An analysis on the process variations - which result in gain and delay mismatches - for a digital transmitter architecture with four bits ensues. The above studies allow RF designers to estimate the number of bits required and the amount of distortion that can be tolerated in the system. Next, a study on the circuit implementation was conducted. A DPA that comprises 7 parallel RF amplifiers driven by a constant RF phase-modulated signal and 7 cascode transistors (individually connected in series with the bottom amplifiers) digitally controlled by a 3-bit digitized envelope signal to reconstruct the UWB signal at the output. Through the use of NFET models from the IBM 130-nm technology, our simulation reveals that our DPA is able to achieve an EVM of - 22 dB. The DPA simulations have been performed at 3.432 GHz centre frequency with a channel bandwidth of 528 MHz, which translates to a fractional bandwidth of 15.4%. Drain efficiencies of 13.2/19.5/21.0% have been obtained while delivering -1.9/2.5/5.5 dBm of output power and consuming 5/9/17 mW of power. In addition, we performed a yield analysis on the digital polar amplifier, based on unit-weighted and binary-weighted architecture, when gain variations are introduced in all the individual stages. The dynamic element matching method is also introduced for the unit-weighted digital polar transmitter. Monte Carlo simulations reveal that when the gain of the amplifiers are allowed to vary at a mean of 1 with a standard deviation of 0.2, the binary-weighted architecture obtained a yield of 79%, while the yields of the unit-weighted architectures are in the neighbourhood of 95%. Moreover, the dynamic element matching technique demonstrates an improvement in the yield by approximately 3%. Finally, a hardware implementation for this architecture based on software-defined arbitrary waveform generators is studied. In this section, we demonstrate that the error vector magnitude results obtained with a four-stage binary-weighted digital polar transmitter under ideal combining conditions fulfill the European Computer Manufacturers Association requirements. The proposed experimental setup, believed to be the first ever attempted, confirm the feasibility of a digital polar transmitter architecture for Ultra-Wideband. In addition, we propose a number of power combining techniques suitable for the hardware implementation. Spatial power combining, in particular, shows a high potential for the digital polar transmitter architecture. The above studies demonstrate the feasibility of the digital polar architecture with good power efficiency for a wideband wireless standard with low-power and high fractional bandwidth requirements

In-field Built-in Self-test for Measuring RF Transmitter Power and Gain

abstract: RF transmitter manufacturers go to great extremes and expense to ensure that their product meets the RF output power requirements for which they are designed. Therefore, there is an urgent need for in-field monitoring of output power and gain to bring down the costs of RF transceiver testing and ensure product reliability. Built-in self-test (BIST) techniques can perform such monitoring without the requirement for expensive RF test equipment. In most BIST techniques, on-chip resources, such as peak detectors, power detectors, or envelope detectors are used along with frequency down conversion to analyze the output of the design under test (DUT). However, this conversion circuitry is subject to similar process, voltage, and temperature (PVT) variations as the DUT and affects the measurement accuracy. So, it is important to monitor BIST performance over time, voltage and temperature, such that accurate in-field measurements can be performed. In this research, a multistep BIST solution using only baseband signals for test analysis is presented. An on-chip signal generation circuit, which is robust with respect to time, supply voltage, and temperature variations is used for self-calibration of the BIST system before the DUT measurement. Using mathematical modelling, an analytical expression for the output signal is derived first and then test signals are devised to extract the output power of the DUT. By utilizing a standard 180nm IBM7RF CMOS process, a 2.4GHz low power RF IC incorporated with the proposed BIST circuitry and on-chip test signal source is designed and fabricated. Experimental results are presented, which show this BIST method can monitor the DUT’s output power with +/- 0.35dB accuracy over a 20dB power dynamic range.Dissertation/ThesisMasters Thesis Electrical Engineering 201

ワイヤレス通信のための先進的な信号処理技術を用いた非線形補償法の研究

The inherit nonlinearity in analogue front-ends of transmitters and receivers have had primary impact on the overall performance of the wireless communication systems, as it gives arise of substantial distortion when transmitting and processing signals with such circuits. Therefore, the nonlinear compensation (linearization) techniques become essential to suppress the distortion to an acceptable extent in order to ensure sufficient low bit error rate. Furthermore, the increasing demands on higher data rate and ubiquitous interoperability between various multi-coverage protocols are two of the most important features of the contemporary communication system. The former demand pushes the communication system to use wider bandwidth and the latter one brings up severe coexistence problems. Having fully considered the problems raised above, the work in this Ph.D. thesis carries out extensive researches on the nonlinear compensations utilizing advanced digital signal processing techniques. The motivation behind this is to push more processing tasks to the digital domain, as it can potentially cut down the bill of materials (BOM) costs paid for the off-chip devices and reduce practical implementation difficulties. The work here is carried out using three approaches: numerical analysis & computer simulations; experimental tests using commercial instruments; actual implementation with FPGA. The primary contributions for this thesis are summarized as the following three points: 1) An adaptive digital predistortion (DPD) with fast convergence rate and low complexity for multi-carrier GSM system is presented. Albeit a legacy system, the GSM, however, has a very strict requirement on the out-of-band emission, thus it represents a much more difficult hurdle for DPD application. It is successfully implemented in an FPGA without using any other auxiliary processor. A simplified multiplier-free NLMS algorithm, especially suitable for FPGA implementation, for fast adapting the LUT is proposed. Many design methodologies and practical implementation issues are discussed in details. Experimental results have shown that the DPD performed robustly when it is involved in the multichannel transmitter. 2) The next generation system (5G) will unquestionably use wider bandwidth to support higher throughput, which poses stringent needs for using high-speed data converters. Herein the analog-to-digital converter (ADC) tends to be the most expensive single device in the whole transmitter/receiver systems. Therefore, conventional DPD utilizing high-speed ADC becomes unaffordable, especially for small base stations (micro, pico and femto). A digital predistortion technique utilizing spectral extrapolation is proposed in this thesis, wherein with band-limited feedback signal, the requirement on ADC speed can be significantly released. Experimental results have validated the feasibility of the proposed technique for coping with band-limited feedback signal. It has been shown that adequate linearization performance can be achieved even if the acquisition bandwidth is less than the original signal bandwidth. The experimental results obtained by using LTE-Advanced signal of 320 MHz bandwidth are quite satisfactory, and to the authors’ knowledge, this is the first high-performance wideband DPD ever been reported. 3) To address the predicament that mobile operators do not have enough contiguous usable bandwidth, carrier aggregation (CA) technique is developed and imported into 4G LTE-Advanced. This pushes the utilization of concurrent dual-band transmitter/receiver, which reduces the hardware expense by using a single front-end. Compensation techniques for the respective concurrent dual-band transmitter and receiver front-ends are proposed to combat the inter-band modulation distortion, and simultaneously reduce the distortion for the both lower-side band and upper-side band signals.電気通信大学201