Proceedings of the Second Caltech Conference on Very Large Scale Integration, held at the California Institute of Technology 19-21 January, 1981 ; Organized by the Caltech Computer Science Department and the Caltech Industrial Associates Office, and sponsored by Caltech Industrial Associates and the National Science Foundation

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Development of an architectural design tool for 3-D VLSI sensors

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Includes bibliographical references (p. 153-159).Three dimensional integration schemes for VLSI have the potential for enabling the development of new high-performance architectures for applications such as focal plane sensors. Due to the high costs involved in 3-D VLSI fabrication and the fabrication complexity of 3-D integration, analysis of the design and process tradeoffs for a particular application is essential. An architectural and topological design tool is presented that enables the high-level analysis and optimization of sensor architectures targeted to a variety of 3-D VLSI process options. This design tool is based on an inference chain evaluation framework, and allows for a high-level structural representation of a circuit architecture to be considered in conjunction with low-level process models. Approximation strategies for projecting circuit area and performance are incorporated into the inference chain relations.by Brian Tyrrell.S.M

InP microdisks for optical signal processing and data transmission

The performance increase in telecommunication and computing systems demands an ever increasing input-output (IO) bandwidth and IO density, which can be met by integrated photonics. Using photonic integration, much higher densities of optical components can be achieved allowing for short-range optical communication systems in, e.g., high performance computers. The key functionalities required for these optical communication systems are light generation, light modulation and light detection. In addition to this other functionalities are also desirable, such as wavelength conversion. This thesis highlights the design and fabrication of indium phosphide (InP) microdisks heterogeneously integrated on silicon-on-insulator substrates. The fabrication of the microdisks in a laboratory clean-room environment is described. These devices can fulfil the above-mentioned functions required in optical communication. Experiments are then performed on the fabricated devices dealing with these various functionalities that are required for optical communication. The lasing properties of the devices are shown and simulated with a spatiallydependent rate equation model accurately predicting the device behaviour. A detailed speed analysis is given, including a parameter extraction of the devices. The operation of the devices as detectors is highlighted. Furthermore the PhD thesis provides a deep analysis of the use of InP microdisks as modulators. Besides the forward-biased operation principle using the free-carrier plasma-dispersion effect, also a high-speed reversely biased operation mode is proposed and demonstrated experimentally. The thesis also describes various approaches on how to improve the performance of the devices, in particular when using them as lasers. Ways how to increase the output power and how to enhance the operation speed are discussed. Because the device is strongly dependent on the coupling between the resonant InP cavity and the silicon waveguide, an extensive analysis of the coupling and the influence of certain process steps on the device performance are given. The PhD thesis concludes the work carried out on InP microdisks and gives an outlook about improving the device performance with respect to specific applications and how to further improve the manufacturability of the devices. Finally, for the InP microdisk-based devices an outlook is given about suitable applications, such as on-chip optical links for instance

Monolithic electronic-photonic integration in state-of-the-art CMOS processes

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Cataloged from student submitted PDF version of thesis.Includes bibliographical references (p. 388-407).As silicon CMOS transistors have scaled, increasing the density and energy efficiency of computation on a single chip, the off-chip communication link to memory has emerged as the major bottleneck within modern processors. Photonic devices promise to break this bottleneck with superior bandwidth-density and energy-efficiency. Initial work by many research groups to adapt photonic device designs to a silicon-based material platform demonstrated suitable independent performance for such links. However, electronic-photonic integration attempts to date have been limited by the high cost and complexity associated with modifying CMOS platforms suitable for modern high-performance computing applications. In this work, we instead utilize existing state-of-the-art electronic CMOS processes to fabricate integrated photonics by: modifying designs to match the existing process; preparing a design-rule compliant layout within industry-standard CAD tools; and locally-removing the handle silicon substrate in the photonic region through post-processing. This effort has resulted in the fabrication of seven test chips from two major foundries in 28, 45, 65 and 90 nm CMOS processes. Of these efforts, a single die fabricated through a widely available 45nm SOI-CMOS mask-share foundry with integrated waveguides with 3.7 dB/cm propagation loss alongside unmodified electronics with less than 5 ps inverter stage delay serves as a proof-of-concept for this approach. Demonstrated photonic devices include high-extinction carrier-injection modulators, 8-channel wavelength division multiplexing filter banks and low-efficiency silicon germanium photodetectors. Simultaneous electronic-photonic functionality is verified by recording a 600 Mb/s eye diagram from a resonant modulator driven by integrated digital circuits. Initial work towards photonic device integration within the peripheral CMOS flow of a memory process that has resulted in polysilicon waveguide propagation losses of 6.4 dB/cm will also be presented.by Jason S. Orcutt.Ph.D

XNAP: A Novel Two-Dimensional X-Ray Detector for Time Resolved Synchrotron Applications

The XNAP project develops a demonstration system for a spatially resolving detector with timing capabilities in the nanosecond range. A dense array of avalanche photodiodes is combined with multiple readout ASICs to build the detector hybrid. On an area of nearly 1 cm2, single photons can be counted within each of the 1k pixels. After 20 years of continuous improvements during operation, the ESRF Synchrotron is going to be upgraded substantially by the replacement of major parts of the source and the beamlines. For experimental techniques that will benefit from the increased brilliance, research into X-ray detectors is required. The requirements for the novel detector are composed of the distinguished properties of multiple state-of-the-art detector systems, shifted towards technical limits. The specification is transferred into the design of the sensor, ASIC, interposing structure and the readout system. A smaller prototype detector is built to resolve implementation challenges ahead of its large-scale accomplishment. Emphasis is put on the ASIC, and parallel approaches for the interconnecting technology and the readout system are carried out. The usability of the smaller prototype system is demonstrated with measurements of microfocus X-ray and Synchrotron light. Parts of the final detector are characterized at the laboratory prior to its commissioning