Suppression of line voltage related distortion in current controlled grid connected inverters

The influence of selected control strategies on the level of low-order current harmonic distortion generated by an inverter connected to a distorted grid is investigated through a combination of theoretical and experimental studies. A detailed theoretical analysis, based on the concept of harmonic impedance, establishes the suitability of inductor current feedback versus output current feedback with respect to inverter power quality. Experimental results, obtained from a purpose-built 500-W, three-level, half-bridge inverter with an L-C-L output filter, verify the efficacy of inductor current as the feedback variable, yielding an output current total harmonic distortion (THD) some 29% lower than that achieved using output current feedback. A feed-forward grid voltage disturbance rejection scheme is proposed as a means to further reduce the level of low-order current harmonic distortion. Results obtained from an inverter with inductor current feedback and optimized feed-forward disturbance rejection show a THD of just 3% at full-load, representing an improvement of some 53% on the same inverter with output current feedback and no feed-forward compensation. Significant improvements in THD were also achieved across the entire load range. It is concluded that the use of inductor current feedback and feed-forward voltage disturbance rejection represent cost–effect mechanisms for achieving improved output current quality

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Nonlinear Analysis of the 2nd Order Digital Phase Locked loop

This paper proposes a rigorous stability criterion for the 2nd order digital phase locked loop (DPLL),with a charge pump phase frequency detector (CP-PFD) component. The Stability boundary is determined using piecewise linear methods to model the non-linear nature of the CP-PFD component block. It calculates the control voltage, after a predetermined number of input reference signal sampling periods, to a small initial voltage offset. Using this piecewise linear model an exact closed form stability criterion is proposed for the second order system. The 2nd order stability boundaries, as defined by the proposed technique, are compared to that of existing linear theory stability boundaries, and display a significant improvement

Rigorous Stability Criterion for Digital Phase Locked Loops

This paper proposes a rigorous stability criterion for an arbitrary order digital phase locked loop (DPLL), with a charge pump phase frequency detector (CP-PFD) component. Stability boundaries for such systems are determined using piecewise linear methods to model the nonlinear nature of the CP-PFD component block. The model calculates the control voltage, after a predetermined number of input reference signal sampling periods, to a small initial voltage offset. This paper, in particular, takes an in-depth look at the second order system. The second order stability boundaries, as defined by the proposed technique, are compared to that of existing linear theory stability boundaries, and display a significant improvement. The applicability of the proposed technique to higher order systems, using a numerically iterative solution, is presented. Finally the proposed methodology is used to determine the stability boundary of a third order system and thus the component values for a stable system. Using these component values the response of the DPLL to an initial control voltage offset is simulated using a circuit level simulation. Index Terms—High Order, Phase Locked Loop, Piecewise Linear, Stability

Rigorous Stability Criterion for Digital Phase Locked Loops

This paper proposes a rigorous stability criterion for an arbitrary order digital phase locked loop (DPLL), with a charge pump phase frequency detector (CP-PFD) component. Stability boundaries for such systems are determined using piecewise linear methods to model the nonlinear nature of the CP-PFD component block. The model calculates the control voltage, after a predetermined number of input reference signal sampling periods, to a small initial voltage offset. This paper, in particular, takes an in-depth look at the second order system. The second order stability boundaries, as defined by the proposed technique, are compared to that of existing linear theory stability boundaries, and display a significant improvement. The applicability of the proposed technique to higher order systems, using a numerically iterative solution, is presented. Finally the proposed methodology is used to determine the stability boundary of a third order system and thus the component values for a stable system. Using these component values the response of the DPLL to an initial control voltage offset is simulated using a circuit level simulation. Index Terms—High Order, Phase Locked Loop, Piecewise Linear, Stability

On conflict-driven reasoning

Automated formal methods and automated reasoning are interconnected, as formal methods generate reasoning problems and incorporate reasoning techniques. For example, formal methods tools employ reasoning engines to find solutions of sets of constraints, or proofs of conjectures. From a reasoning perspective, the expressivity of the logical language is often directly proportional to the difficulty of the problem. In propositional logic, Conflict-Driven Clause Learning (CDCL) is one of the key features of state-of-the-art satisfiability solvers. The idea is to restrict inferences to those needed to explain conflicts, and use conflicts to prune a backtracking search. A current research direction in automated reasoning is to generalize this notion of conflict-driven satisfiability to a paradigm of conflict-driven reasoning in first-order theories for satisfiability modulo theories and assignments, and even in full first-order logic for generic automated theorem proving. While this is a promising and exciting lead, it also poses formidable challenges

Analysis and design of a second-order digital phase-locked loop

A specific second-order digital phase-locked loop (DPLL) was modeled as a first-order Markov chain with alternatives. From the matrix of transition probabilities of the Markov chain, the steady-state phase error of the DPLL was determined. In a similar manner the loop's response was calculated for a fading input. Additionally, a hardware DPLL was constructed and tested to provide a comparison to the results obtained from the Markov chain model. In all cases tested, good agreement was found between the theoretical predictions and the experimental data