17,574 research outputs found
Silicene Nanomesh
Similar to graphene, zero band gap limits the application of silicene in
nanoelectronics despite of its high carrier mobility. By using first-principles
calculations, we reveal that a band gap is opened in silicene nanomesh (SNM)
when the width W of the wall between the neighboring holes is even. The size of
the band gap increases with the reduced W and has a simple relation with the
ratio of the removed Si atom and the total Si atom numbers of silicene. Quantum
transport simulation reveals that the sub-10 nm single-gated SNM field effect
transistors show excellent performance at zero temperature but such a
performance is greatly degraded at room temperature
Weighted p-bits for FPGA implementation of probabilistic circuits
Probabilistic spin logic (PSL) is a recently proposed computing paradigm
based on unstable stochastic units called probabilistic bits (p-bits) that can
be correlated to form probabilistic circuits (p-circuits). These p-circuits can
be used to solve problems of optimization, inference and also to implement
precise Boolean functions in an "inverted" mode, where a given Boolean circuit
can operate in reverse to find the input combinations that are consistent with
a given output. In this paper we present a scalable FPGA implementation of such
invertible p-circuits. We implement a "weighted" p-bit that combines stochastic
units with localized memory structures. We also present a generalized tile of
weighted p-bits to which a large class of problems beyond invertible Boolean
logic can be mapped, and how invertibility can be applied to interesting
problems such as the NP-complete Subset Sum Problem by solving a small instance
of this problem in hardware
Phase-tunable Josephson thermal router
Since the the first studies of thermodynamics, heat transport has been a
crucial element for the understanding of any thermal system. Quantum mechanics
has introduced new appealing ingredients for the manipulation of heat currents,
such as the long-range coherence of the superconducting condensate. The latter
has been exploited by phase-coherent caloritronics, a young field of
nanoscience, to realize Josephson heat interferometers, which can control
electronic thermal currents as a function of the external magnetic flux. So
far, only one output temperature has been modulated, while multi-terminal
devices that allow to distribute the heat flux among different reservoirs are
still missing. Here, we report the experimental realization of a phase-tunable
thermal router able to control the heat transferred between two terminals
residing at different temperatures. Thanks to the Josephson effect, our
structure allows to regulate the thermal gradient between the output electrodes
until reaching its inversion. Together with interferometers, heat diodes and
thermal memories, the thermal router represents a fundamental step towards the
thermal conversion of non-linear electronic devices, and the realization of
caloritronic logic components.Comment: 9 pages, 5 figure
Designing energy-efficient sub-threshold logic circuits using equalization and non-volatile memory circuits using memristors
The very large scale integration (VLSI) community has utilized aggressive complementary metal-oxide semiconductor (CMOS) technology scaling to meet the ever-increasing performance requirements of computing systems. However, as we enter the nanoscale regime, the prevalent process variation effects degrade the CMOS device reliability. Hence, it is increasingly essential to explore emerging technologies which are compatible with the conventional CMOS process for designing highly-dense memory/logic circuits. Memristor technology is being explored as a potential candidate in designing non-volatile memory arrays and logic circuits with high density, low latency and small energy consumption. In this thesis, we present the detailed functionality of multi-bit 1-Transistor 1-memRistor (1T1R) cell-based memory arrays. We present the performance and energy models for an individual 1T1R memory cell and the memory array as a whole. We have considered TiO2- and HfOx-based memristors, and for these technologies there is a sub-10% difference between energy and performance computed using our models and HSPICE simulations. Using a performance-driven design approach, the energy-optimized TiO2-based RRAM array consumes the least write energy (4.06 pJ/bit) and read energy (188 fJ/bit) when storing 3 bits/cell for 100 nsec write and 1 nsec read access times. Similarly, HfOx-based RRAM array consumes the least write energy (365 fJ/bit) and read energy (173 fJ/bit) when storing 3 bits/cell for 1 nsec write and 200 nsec read access times.
On the logic side, we investigate the use of equalization techniques to improve the energy efficiency of digital sequential logic circuits in sub-threshold regime. We first propose the use of a variable threshold feedback equalizer circuit with combinational logic blocks to mitigate the timing errors in digital logic designed in sub-threshold regime. This mitigation of timing errors can be leveraged to reduce the dominant leakage energy by scaling supply voltage or decreasing the propagation delay. At the fixed supply voltage, we can decrease the propagation delay of the critical path in a combinational logic block using equalizer circuits and, correspondingly decrease the leakage energy consumption. For a 8-bit carry lookahead adder designed in UMC 130 nm process, the operating frequency can be increased by 22.87% (on average), while reducing the leakage energy by 22.6% (on average) in the sub-threshold regime. Overall, the feedback equalization technique provides up to 35.4% lower energy-delay product compared to the conventional non-equalized logic. We also propose a tunable adaptive feedback equalizer circuit that can be used with sequential digital logic to mitigate the process variation effects and reduce the dominant leakage energy component in sub-threshold digital logic circuits. For a 64-bit adder designed in 130 nm our proposed approach can reduce the normalized delay variation of the critical path delay from 16.1% to 11.4% while reducing the energy-delay product by 25.83% at minimum energy supply voltage. In addition, we present detailed energy-performance models of the adaptive feedback equalizer circuit. This work serves as a foundation for the design of robust, energy-efficient digital logic circuits in sub-threshold regime
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