Energy-aware embedded media processing: customizable memory subsystems and energy management policies

textThe design of energy-efficient data memory architectures for embedded system platforms has received considerable attention in recent years. In this dissertation we propose a special-purpose data memory subsystem, called Xtream-Fit, targeted to streaming media applications executing on both generic uniprocessor embedded platforms and powerful SMT-based multi-threading platforms. We empirically demonstrate that Xtream-Fit achieves high energydelay efficiency across a wide range of media devices, from systems running a single media application to systems concurrently executing multiple media applications under synchronization constraints. Xtream-Fit’s energy efficiency is predicated on a novel task-based execution model that exposes/enhances opportunities for efficient prefetching, and aggressive dynamic energy conservation techniques targeting on-chip and off-chip memory components. A key novelty of Xtream-Fit is that it exposes a single customization parameter, thus enabling a very simple and yet effective design space exploration methodology to find the best memory configuration for the target application(s). Extensive experimental results show that Xtream-Fit reduces energy-delay product substantially – by 32% to 69% – as compared to ‘standard’ general-purpose memory subsystems enhanced with state of the art cache decay and SDRAM power mode control policies.Electrical and Computer Engineerin

Dynamic Voltage Scaling for Energy- Constrained Real-Time Systems

The problem of reducing energy consumption is dominating the design of several real-time systems. The Dynamic Voltage Scaling (DVS) technique, provided by most microprocessors, allow to balance computational speed versus energy consumption. We present some novel energy-aware scheduling algorithms that allow to expoit this technique while meeting real-time constraints. In particular, we present the GRUB-PA algorithm which, unlike most existing algorithms, allows to reduce energy consumption on real-time systems consisting of any kind of task. We also present a working implementation of the algorithm on Linux

Scheduling Data Delivery in Heterogeneous Wireless Sensor Networks

In this paper we present a proxy-level scheduler that can significantly improve QoS in heterogeneous wireless sensor networks while at the same time reducing the overall power consumption. Our scheduler is transparent to both applications and MAC in order to take the advantage of the standard off-the-shelf components. The proposed scheduling reduces collisions through a generalized TDMA implementation, and thus improves throughput and QoS, by activating only a subset of stations at a time. Power savings are achieved by scheduling transfer of larger bursts of IP packets followed by longer idle periods during which node’s radio can either enter sleep or be turned off. Our simulation and measurement results show significant power savings with an improvement in QoS. On average we get 18% of saturation throughput enhancement for real traffic and 79 % of power reduction in a highly loaded network

Energy efficient scheduling for hard real-time systems

Für moderne elektronische Systeme spielt der Energieverbrauch eine immer wichtigere Rolle. Geringer Stromverbrauch und lange Akkulaufzeit sind die wichtigsten Anforderungen bei der Entwicklung, um die Betriebskosten der Geräte zu reduzieren. Auf Systemebene gibt es zwei weit verbreitete Techniken, um den Energieverbrauch zu reduzieren: Dynamic Power Management (DPM) und Dynamic Voltage and Frequency Scaling (DVS). Beide Techniken sind in der Lage, den Trade-off zwischen Systemleistung und Stromverbrauch zu regulieren. Da beide Techniken den Energieverbrauch auf Kosten der Systemleistung reduzieren, sollten sie insbesondere in der Kombination mit Echtzeitsystemen mit Bedacht eingesetzt werden. Um den Energieverbrauch in Echtzeitsystemen zu reduzieren, beschäftigt sich diese Arbeit mit dem Problem der Energieverbrauchsoptimierung mit Hilfe einer kombinierten Anwendung von DPM und DVS. Hiermit wird insbesondere der Aufwand beim Zustandswechsel für DPM und DVS untersucht. Leider ist das betrachtete Optimierungsproblem NP-hart, sodass für seine Lösung keine effizienten Algorithmen existieren. Daher wird in dieser Dissertation ein heuristischer Suchalgorithmus entwickelt, der den Simulated Annealing Algorithmus um spezielle Regeln für die Selektion von Nachbarn erweitert. Darüber hinaus wird eine auf Regression basierte Technik zur Analyse des Verhaltens des vorgestellten Algorithmus erarbeitet. Ferner präsentiert diese Arbeit einen Ansatz zur Onlineausführung des vorgestellten Algorithmus. Dabei besteht die größte Herausforderung darin, dass der heuristische Algorithmus in der Ausführung des Echtzeitsystems integriert werden muss. Dadurch ist das System in der Lage, sich selbstständig an dynamische Veränderungen anzupassen. Noch wichtiger ist jedoch der geführte Nachweis, dass der Laufzeitaufwand der Onlineausführung gering ist.In modern electronic systems, especially in battery-driven devices, energy consumption has clearly become one of the most important design concerns. Low power consumption and long battery life are major development requirements and objectives to reduce system operation cost. From the system-level point of view, there are two widely applied energy saving techniques, Dynamic Power Management (DPM) and Dynamic Voltage and Frequency Scaling (DVS), which are able to adjust the trade-off between system performance and power consumption. Both techniques reduce system power consumption at the cost of performance loss, which is a crucial point in the context of hard real-time systems. To address energy optimization problem, this dissertation studies in detail the combined application of DPM and DVS on both single- and multi-core processor platforms, in particular with non-negligible state switching overhead. Unfortunately, the facing problem is proven to be NP-hard in the strong sense, which indicates non-existence of efficient algorithms. Thus, this work proposes a heuristic search algorithm by extending simulated annealing with neighbor selection guidelines using domain specific information. In addition, a regression based mechanism to predict algorithm run-time behavior is proposed, which in turn is used for quality estimation of a solution and derivation of an efficient termination criterion. Furthermore, this dissertation presents an approach, which is able to run the proposed algorithms in a completely online fashion. Hereby, the main challenge is to integrate the heuristic into the execution of real-time tasks, which is solved by mapping iterations of the algorithm to hyper periods of the task execution. In doing so, a system becomes self-adaptive to dynamic changes. More importantly, it can be shown that the run-time overhead of this approach is provably low.Tag der Verteidigung: 20.12.2013Paderborn, Univ., Diss., 201

Power management for interactive 3D games

Ph.DDOCTOR OF PHILOSOPH

The Interplay of Reward and Energy in Real-Time Systems

This work contends that three constraints need to be addressed in the context of power-aware real-time systems: energy, time and task rewards/values. These issues are studied for two types of systems. First, embedded systems running applications that will include temporal requirements (e.g., audio and video). Second, servers and server clusters that have timing constraints and Quality of Service (QoS) requirements implied by the application being executed (e.g., signal processing, audio/video streams, webpages). Furthermore, many future real-time systems will rely on different software versions to achieve a variety of QoS-aware tradeoffs, each with different rewards, time and energy requirements.For hard real-time systems, solutions are proposed that maximize the system reward/profit without exceeding the deadlines and without depleting the energy budget (in portable systems the energy budget is determined by the battery charge, while in server farms it is dependent on the server architecture and heat/cooling constraints). Both continuous and discrete reward and power models are studied, and the reward/energy analysis is extended with multiple task versions, optional/mandatory tasks and long-term reward maximization policies.For soft real-time systems, the reward model is relaxed into a QoS constraint, and stochastic schemes are first presented for power management of systems with unpredictable workloads. Then, load distribution and power management policies are addressed in the context of servers and homogeneous server farms. Finally, the work is extended with QoS-aware local and global policies for the general case of heterogeneous systems

Flexi-WVSNP-DASH: A Wireless Video Sensor Network Platform for the Internet of Things

abstract: Video capture, storage, and distribution in wireless video sensor networks (WVSNs) critically depends on the resources of the nodes forming the sensor networks. In the era of big data, Internet of Things (IoT), and distributed demand and solutions, there is a need for multi-dimensional data to be part of the Sensor Network data that is easily accessible and consumable by humanity as well as machinery. Images and video are expected to become as ubiquitous as is the scalar data in traditional sensor networks. The inception of video-streaming over the Internet, heralded a relentless research for effective ways of distributing video in a scalable and cost effective way. There has been novel implementation attempts across several network layers. Due to the inherent complications of backward compatibility and need for standardization across network layers, there has been a refocused attention to address most of the video distribution over the application layer. As a result, a few video streaming solutions over the Hypertext Transfer Protocol (HTTP) have been proposed. Most notable are Apple’s HTTP Live Streaming (HLS) and the Motion Picture Experts Groups Dynamic Adaptive Streaming over HTTP (MPEG-DASH). These frameworks, do not address the typical and future WVSN use cases. A highly flexible Wireless Video Sensor Network Platform and compatible DASH (WVSNP-DASH) are introduced. The platform's goal is to usher video as a data element that can be integrated into traditional and non-Internet networks. A low cost, scalable node is built from the ground up to be fully compatible with the Internet of Things Machine to Machine (M2M) concept, as well as the ability to be easily re-targeted to new applications in a short time. Flexi-WVSNP design includes a multi-radio node, a middle-ware for sensor operation and communication, a cross platform client facing data retriever/player framework, scalable security as well as a cohesive but decoupled hardware and software design.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

CROSS-LAYER CUSTOMIZATION PLATFORM FOR LOW-POWER AND REAL-TIME EMBEDDED APPLICATIONS

Modern embedded applications have become increasingly complex and diverse in their functionalities and requirements. Data processing, communication and multimedia signal processing, real-time control and various other functionalities can often need to be implemented on the same System-on-Chip(SOC) platform. The significant power constraints and real-time guarantee requirements of these applications have become significant obstacles for the traditional embedded system design methodologies. The general-purpose computing microarchitectures of these platforms are designed to achieve good performance on average, which is far from optimal for any particular application. The system must always assume worst-case scenarios, which results in significant power inefficiencies and resource under-utilization. This dissertation introduces a cross-layer application-customizable embedded platform, which dynamically exploits application information and fine-tunes system components at system software and hardware layers. This is achieved with the close cooperation and seamless integration of the compiler, the operating system, and the hardware architecture. The compiler is responsible for extracting application regularities through static and profile-based analysis. The relevant application knowledge is propagated and utilized at run-time across the system layers through the judiciously introduced reconfigurability at both OS and hardware layers. The introduced framework comprehensively covers the fundamental subsystems of memory management and multi-tasking execution control

Providing QoS with Reduced Energy Consumption via Real-Time Voltage Scaling on Embedded Systems

Low energy consumption has emerged as one of the most important design objectives for many modern embedded systems, particularly the battery-operated PDAs. For some soft real-time applications such as multimedia applications, occasional deadline misses can be tolerated. How to leverage this feature to save more energy while still meeting the user required quality of service (QoS) is the research topic this thesis focuses on. We have proposed a new probabilistic design methodology, a set of energy reduction techniques for single and multiple processor systems by using dynamic voltage scaling (DVS), the practical solutions to voltage set-up problem for multiple voltage DVS system, and a new QoS metric. Most present design space exploration techniques, which are based on application's worst case execution time, often lead to over-designing systems. We have proposed the probabilistic design methodology for soft real-time embedded systems by using detailed execution time information in order to reduce the system resources while delivering the user required QoS probabilistically. One important phase in the probabilistic design methodology is the offline/online resource management. As an example, we have proposed a set of energy reduction techniques by employing DVS techniques to exploit the slacks arising from the tolerance to deadline misses for single and multiple processor systems while meeting the user required completion ratio statistically. Multiple-voltage DVS system is predicted as the future low-power system by International Technology Roadmap for Semiconductors (ITRS). In order to find the best way to employ DVS, we have formulated the voltage set-up problem and provided its practical solutions that seek the most energy efficient voltage setting for the design of multiple-voltage DVS systems. We have also presented a case study in designing energy-efficient dual voltage soft real-time system with (m, k)-firm deadline guarantee. Although completion ratio is widely used as a QoS metric, it can only be applied to the applications with independent tasks. We have proposed a new QoS metric that differentiates firm and soft deadlines and considers the task dependency as well. Based on this new metric, we have developed a set of online scheduling algorithms that enhance quality of presentation (QoP) significantly, particularly for overloaded systems

Gestión de la carga dinámica de tareas de tiempo real con criterios de ahorro energético y su aplicación en el desarrollo de un middleware de control

[EN] The development of embedded systems in industrial sectors such as railway, aerospace and automotive are based on Critical Real-Time Embedded Systems (CRTES). These systems face new challenges and demand related to increase of dependability, intelligence, connectivity, cost-size-volume reduction and energy efficiency. In this last topic is where this thesis expects to have a higher contribution. The global energy consumption can be combined with others criteria such as schedulability, communication delays and control application correctness, which contribute to determine the dynamic code movement and on-line load balancing in a system. The main goal of this thesis is the development of mechanisms for the management and optimization of energy consumption. These mechanisms are presented in the context of a distributed real-time control system and from the perspective of control kernel middleware. Let's consider a dynamic environment where an embedded and networked system operates with the support of task migration and processor frequency scaling. Assuming that the system knows where and when it must allocate tasks, we must perform feasibility analyses when each task arrives and departs on the affected embedded units. This guarantees that the temporal requirements of the system will be accomplished during the task allocation phase or delegation of tasks. Additionally, a new processor speed (frequency scaling) should be also computed to enable the system to adapt itself to the new computational workload and reduce energy consumption. And in this last is where the proposed algorithms in this work have their higher relevance. Although some authors have carried out these two phases (feasibility analysis and frequency scaling computation) separately, these analyses are strongly related and in some cases can be performed together. In this thesis, we present novel algorithm that perform feasibility analyses and compute new processor static frequencies based on dynamic voltage and frequency scaling techniques (DVFS). The frequency obtained as result of applying the algorithm proposed is the minimum processor frequency that minimizes CPU energy consumption while guaranteeing the fulfilment of real-time system constraints. The algorithm uses fixed priority scheduling schemes with deadlines less than, or equal to, the period of the tasks. Other propose of this algorithm is the use on-line during the task allocation and processor speed assignment phases. In this work, the computation of the minimum static processor frequency is accompanied with the proposed the additional approaches for the dynamic optimization of the energy consumption. Dynamic algorithms are based on the reclamation of additional slack resulting from the early completions of tasks. These are then used to further reduce the processor frequency and save more energy. These algorithms are applied at run-time. The computation of these additional dynamic processor frequencies uses as reference the previous calculation of the minimum static processor frequency. Through extensive simulations, we evaluate the performance of this algorithm against other existing feasibility tests that have been adapted to compute the minimum processor frequency. This minimum frequency is computed in terms of energy consumption, acceptability ratio, and real computing costs. In addition, predictability in the execution and behaviour of the algorithms in relation to the continuing arrival of tasks is analysed.[ES] El desarrollo de sistemas de cómputo en sectores industriales tales como el ferroviario, aeroespacial y automóvil está basado en Sistemas Empotrados Críticos de Tiempo Real (CRTES). Estos sistemas se enfrentan a nuevas demandas y exigencias relacionadas con el incremento de la fiabilidad, mayor inteligencia, conectividad, reducción del volumen, mejoras del rendimiento y eficiencia en el consumo energético. Y es en ese último aspecto donde esta tesis doctoral espera hacer su principal aportación. El criterio de consumo energético, combinado con otros criterios tales como planificabilidad, retardos de comunicación y estabilidad en aplicaciones de control, contribuyen a la determinación del movimiento de código y al balance de cargas en sistemas distribuidos. El objetivo principal de esta tesis es el desarrollo de mecanismos de gestión y optimización del consumo energético. Estos mecanismos se presentan como posibles funcionalidades en el marco del diseño de middlewares basados en el concepto de núcleo de control. El desarrollo de esta tesis considera un entorno dinámico donde sistemas CRTES, basados en soportes middleware y conectados a una red de comunicaciones, permiten llevar a cabo migraciones de tareas y modificaciones de la frecuencia del procesador en tiempo de ejecución. Suponiendo que el sistema distribuido conoce dónde y cuándo asignar las tareas entre las unidades de cómputo, es necesario realizar un análisis de factibilidad de la planificación en cada llegada y partida de tareas sobre los sistemas empotrados afectados. De esta forma, se garantiza que los requisitos temporales del sistema serán cumplidos durante la fase de re-asignación o distribución de tareas. Esto también implica que una nueva velocidad de procesador (escalamiento de frecuencia) deberá ser calculada para permitir una optimización energética y la adaptación del sistema a las nuevas condiciones de carga computacional. Y es en este punto en el que los algoritmos propuestos en esta tesis tiene su importancia. Aunque algunos autores han llevado a cabo estas dos fases (análisis de planificabilidad y cálculo del escalado de frecuencia) separadamente, estos análisis están fuertemente relacionados y en algunos casos pueden ser ejecutados de forma conjunta. En este trabajo de tesis se propone un algoritmo nuevo para el análisis de factibilidad de planificación y el cálculo de frecuencias estáticas de procesador basado en técnicas de escalamiento de frecuencia y voltaje dinámico (también conocido como DVFS). La frecuencia obtenida por este algoritmo es la frecuencia mínima que garantiza que si se usa de forma invariable en el procesador, se ahorrará la mayor energía posible y además se cumplirán todos los plazos de ejecución de las tareas del sistema. Este algoritmo utiliza un esquema de planificación por prioridades fijas con plazos de ejecución menor y/o igual que el periodo de las tareas. Uno de los propósitos de este algoritmo es su uso durante la ejecución del sistema, que permita gestionar adaptaciones de carga computacional y energética del procesador. El algoritmo para el cálculo de frecuencias estáticas de procesador, es complementado en esta tesis con la propuesta de métodos nuevos de optimización dinámica, que ajustan el consumo energético basado en las condiciones de carga de computo reales en cada instante. Estos métodos propuestos se utilizan en tiempo de ejecución de las tareas del sistema y se basan en la asignación de frecuencias dinámicas al procesador. Estas nuevas frecuencias utilizan como referencia el cálculo previo de la frecuencia estática. Los cambios de frecuencia dinámicos se suceden como respuesta a instantes ociosos de procesador debidos principalmente a terminaciones anticipadas de tareas. Para la evaluación de esta tesis se proponen un conjunto de simulaciones y experimentos que permiten comparar y valorar las contribuciones de esta tesis con respecto a otros al[CA] El desenvolupament de sistemes de còmput en sectors industrials com són el ferroviari, aeroespacial i automòbil està basat en Sistemes Embeguts Crítics de Temps Real (també coneguts per les sigles en anglès CRTES). Aquests sistemes s'enfronten a noves demandes i exigències relacionades amb l'increment de la fiabilitat, major intel·ligència, connectivitat, reducció del volum, millores de rendiment i eficiència en el consum energètic. És en aquest últim aspecte on aquesta tesi doctoral espera fer la seva principal aportació. El criteri de consum energètic, combinat amb altres criteris com ara planificabilitat, retards de comunicació i estabilitat en aplicacions de control, contribueixen a la determinació del moviment de codi i al balanç de càrregues en sistemes distribuïts. L'objectiu principal d'aquesta tesi és el desenvolupament de mecanismes de gestió i optimització del consum energètic. Aquests mecanismes es presenten com a possibles funcionalitats en el marc del disseny de middlewares basats en el concepte de nucli de control. El desenvolupament d'aquesta tesi considera un entorn dinàmic on sistemes CRTES basats en suport middleware i connectats a una xarxa de comunicacions, permeten dur a terme migracions de tasques i modificacions de la freqüència del processador en temps d'execució. Suposant que el sistema distribuït coneix on i quan assignar les tasques entre les unitats de còmput, cal fer un anàlisi de factibilitat de la planificació en cada arribada i sortida de tasques sobre els sistemes embeguts afectats. D'aquesta manera, es pot garantir que els requisits temporals del sistema seran complerts durant la fase de re-assignació o distribució de tasques. Això també implica que una velocitat de processador nova (escalament de freqüència) ha de ser calculada per permetre una optimització energètica i l'adaptació del sistema a les noves condicions de càrrega computacional. I és en aquest punt en el que els algoritmes proposats en aquesta tesi tenen la seva importància. Encara que alguns autors han dut a terme aquestes dues fases (l'anàlisi de planificabilitat i el càlcul de l'escalat de freqüència) separadament, aquestes anàlisis estan fortament relacionats i en alguns casos poden ser executats de forma conjunta. En aquest treball de tesi es proposa un algoritme nou per a l'anàlisi de factibilitat de planificació i el càlcul de freqüències estàtiques de processador basat en tècniques d'escalament de freqüència i voltatge dinàmic (també conegut com DVFS). La freqüència obtinguda per aquest algoritme és la freqüència mínima que garanteix que si es fa servir de forma invariable en el processador, s'estalviarà la major energia possible i a més a més es compliran tots els terminis d'execució de les tasques del sistema. Aquest algoritme utilitza un esquema de planificació per prioritats fixes amb terminis d'execució menors i/o iguals que el període de les tasques. Un dels propòsits d'aquest algoritme és el seu ús durant l'execució del sistema, que ha de permetre gestionar adaptacions de càrrega computacional i energètica del processador. L'algoritme de càlcul de freqüències estàtiques de processador, és complementat en aquesta tesi amb la proposta de mètodes nous d'optimització dinàmica, que ajusten el consum energètic basat en les condicions de càrregues de còmputs reals en cada instant. Aquests mètodes proposats s'utilitzen en temps d'execució de les tasques del sistema i es basen en l'assignació de freqüències dinàmiques al processador. Aquestes noves freqüències utilitzen com a referència el càlcul previ de la freqüència estàtica. Els canvis de freqüència dinàmics se succeeixen com a resposta a instants ociosos de processador deguts principalment a terminacions anticipades de tasques. Per a l'avaluació d'aquesta tesi es proposen un conjunt de simulacions i experiments que permeten comparar i valorar les contribucionsCoronel Parada, JO. (2016). Gestión de la carga dinámica de tareas de tiempo real con criterios de ahorro energético y su aplicación en el desarrollo de un middleware de control [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/62691TESI