5 research outputs found
Solid State Circuits Technologies
The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book
FDSOI Design using Automated Standard-Cell-Grained Body Biasing
With the introduction of FDSOI processes at competitive technology nodes, body biasing on an unprecedented scale was made possible. Body biasing influences one of the central transistor characteristics, the threshold voltage. By being able to heighten or lower threshold voltage by more than 100mV, the very physics of transistor switching can be manipulated at run time. Furthermore, as body biasing does not lead to different signal levels, it can be applied much more fine-grained than, e.g., DVFS. With the state of the art mainly focused on combinations of body biasing with DVFS, it has thus ignored granularities unfeasible for DVFS. This thesis fills this gap by proposing body bias domain partitioning techniques and for body bias domain partitionings thereby generated, algorithms that search for body bias assignments. Several different granularities ranging from entire cores to small groups of standard cells were examined using two principal approaches: Designer aided pre-partitioning based determination of body bias domains and a first-time, fully automatized, netlist based approach called domain candidate exploration. Both approaches operate along the lines of activation and timing of standard cell groups. These approaches were evaluated using the example of a Dynamically Reconfigurable Processor (DRP), a highly efficient category of reconfigurable architectures which consists of an array of processing elements and thus offers many opportunities for generalization towards many-core architectures. Finally, the proposed methods were validated by manufacturing a test-chip. Extensive simulation runs as well as the test-chip evaluation showed the validity of the proposed methods and indicated substantial improvements in energy efficiency compared to the state of the art. These improvements were accomplished by the fine-grained partitioning of the DRP design. This method allowed reducing dynamic power through supply voltage levels yielding higher clock frequencies using forward body biasing, while simultaneously reducing static power consumption in unused parts.Die Einführung von FDSOI Prozessen in gegenwärtigen Prozessgrößen ermöglichte die Nutzung von Substratvorspannung in nie zuvor dagewesenem Umfang. Substratvorspannung beeinflusst unter anderem eine zentrale Eigenschaft von Transistoren, die Schwellspannung. Mittels Substratvorspannung kann diese um mehr als 100mV erhöht oder gesenkt werden, was es ermöglicht, die schiere Physik des Schaltvorgangs zu manipulieren. Da weiterhin hiervon der Signalpegel der digitalen Signale unberührt bleibt, kann diese Technik auch in feineren Granularitäten angewendet werden, als z.B. Dynamische Spannungs- und Frequenz Anpassung (Engl. Dynamic Voltage and Frequency Scaling, Abk. DVFS). Da jedoch der Stand der Technik Substratvorspannung hauptsächlich in Kombinationen mit DVFS anwendet, werden feinere Granularitäten, welche für DVFS nicht mehr wirtschaftlich realisierbar sind, nicht berücksichtigt. Die vorliegende Arbeit schließt diese Lücke, indem sie Partitionierungsalgorithmen zur Unterteilung eines Entwurfs in Substratvorspannungsdomänen vorschlägt und für diese hierdurch unterteilten Domänen entsprechende Substratvorspannungen berechnet. Hierzu wurden verschiedene Granularitäten berücksichtigt, von ganzen Prozessorkernen bis hin zu kleinen Gruppen von Standardzellen. Diese Entwürfe wurden dann mit zwei verschiedenen Herangehensweisen unterteilt: Chipdesigner unterstützte, vorpartitionierungsbasierte Bestimmung von Substratvorspannungsdomänen, sowie ein erstmals vollautomatisierter, Netzlisten basierter Ansatz, in dieser Arbeit Domänen Kandidaten Exploration genannt. Beide Ansätze funktionieren nach dem Prinzip der Aktivierung, d.h. zu welchem Zeitpunkt welcher Teil des Entwurfs aktiv ist, sowie der Signallaufzeit durch die entsprechenden Entwurfsteile. Diese Ansätze wurden anhand des Beispiels Dynamisch Rekonfigurierbarer Prozessoren (DRP) evaluiert. DRPs stellen eine Klasse hocheffizienter rekonfigurierbarer Architekturen dar, welche hauptsächlich aus einem Feld von Rechenelementen besteht und dadurch auch zahlreiche Möglichkeiten zur Verallgemeinerung hinsichtlich Many-Core Architekturen zulässt. Schließlich wurden die vorgeschlagenen Methoden in einem Testchip validiert. Alle ermittelten Ergebnisse zeigen im Vergleich zum Stand der Technik drastische Verbesserungen der Energieeffizienz, welche durch die feingranulare Unterteilung in Substratvorspannungsdomänen erzielt wurde. Hierdurch konnten durch die Anwendung von Substratvorspannung höhere Taktfrequenzen bei gleicher Versorgungsspannung erzielt werden, während zeitgleich in zeitlich unkritischen oder ungenutzten Entwurfsteilen die statische Leistungsaufnahme minimiert wurde
Scaling and variability in ultra thin body silicon on insulator (UTB SOI) MOSFETs
The main objective of this thesis is to perform a comprehensive simulation study of the
statistical variability in well scaled fully depleted ultra thin body silicon on insulator
(FD-UTB SOI) at nanometer regime. It describes the design procedure for template FDUTB
SOI transistor scaling and the impacts of statistical variability and reliability the
scaled template transistor.
The starting point of this study is a systematic simulation analysis based on a welldesigned
32nm thin body SOI template transistor provided by the FP7 project
PULLNANO. The 32nm template transistor is consistent with the International
Technology Roadmap for Semiconductor (ITRS) 2009 specifications. The wellestablished
3D ‘atomistic’ simulator GARAND has been employed in the designing of
the scaled transistors and to carry out the statistical variability simulations. Following
the foundation work in characterizing and optimizing the template 32 nm gate length
transistor, the scaling proceeds down to 22 nm, 16 nm and 11 nm gate lengths using
typically 0.7 scaling factor in respect of the horizontal and vertical transistor
dimensions. The device design process is targeted for low power applications with a
careful consideration of the impacts of the design parameters choice including buried
oxide thickness (TBOX), source/drain doping abruptness (σ) and spacer length (Lspa). In
order to determine the values of TBOX, σ, and Lspa, it is important to analyze simulation
results, carefully assessing the impact on manufacturability and to consider the
corresponding trade-off between short channel effects and on-current performance.
Considering the above factors, TBOX = 10nm, σ = 2nm/dec and Lspa = 7nm have been
adopted as optimum values respectively.
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The statistical variability of the transistor characteristics due to intrinsic parameter
fluctuation (IPF) in well-scaled FD-UTB SOI devices is systematically studied for the
first time. The impact of random dopant fluctuation (RDF), line edge roughness (LER)
and metal gate granularity (MGG) on threshold voltage (Vth), on-current (Ion) and drain
induced barrier lowering (DIBL) are analysed. Each principal sources of variability is
treated individually and in combination with other variability sources in the simulation
of large ensembles of microscopically different devices. The introduction of highk/
metal gate stack has improved the electrostatic integrity and enhanced the overall
device performance. However, in the case of fully depleted channel transistors, MGG
has become a dominant variability factor for all critical electrical parameters at gate first
technology. For instance, σVth due to MGG increased to 41.9 mV at 11nm gate length
compared to 26.0 mV at 22nm gate length. Similar trend has also been observed in σIon,
increasing from 0.065 up to 0.174 mA/μm when the gate length is reduced from 22 nm
down to 11 nm. Both RDF and LER have significant role in the intrinsic parameter
fluctuations and therefore, none of these sources should be overlooked in the
simulations.
Finally, the impact of different variability sources in combination with positive bias
temperature instability (PBTI) degradation on Vth, Ion and DIBL of the scaled
nMOSFETs is investigated. Our study indicates that BTI induced charge trapping is a
crucial reliability problem for the FD-UTB SOI transistors operation. Its impact not
only introduces a significant degradation of transistor performance, but also accelerates
the statistical variability. For example, the effect of a late degradation stage (at trap
density of 1e12/cm2) in the presence of RDF, LER and MGG results in σVth increase to
36.9 mV, 45.0 mV and 58.3 mV for 22 nm, 16 nm and 11 nm respectively from the
original 29.0 mV, 37.9 mV and 50.4 mV values in the fresh transistors
Characterisation of thermal and coupling effects in advanced silicon MOSFETs
PhD ThesisNew approaches to metal-oxide-semiconductor field effect transistor (MOSFET)
engineering emerge in order to keep up with the electronics market demands. Two main
candidates for the next few generations of Moore’s law are planar ultra-thin body and
buried oxide (UTBB) devices and three-dimensional FinFETs. Due to miniature
dimensions and new materials with low thermal conductivity, performance of advanced
MOSFETs is affected by self-heating and substrate effects. Self-heating results in an
increase of the device temperature which causes mobility reduction, compromised
reliability and signal delays. The substrate effect is a parasitic source and drain coupling
which leads to frequency-dependent analogue behaviour. Both effects manifest
themselves in the output conductance variation with frequency and impact analogue as
well as digital performance. In this thesis self-heating and substrate effects in FinFETs
and UTBB devices are characterised, discussed and compared. The results are used to
identify trade-offs in device performance, geometry and thermal properties. Methods
how to optimise the device geometry or biasing conditions in order to minimise the
parasitic effects are suggested.
To identify the most suitable technique for self-heating characterisation in advanced
semiconductor devices, different methods of thermal characterisation (time and
frequency domain) were experimentally compared and evaluated alongside an analytical
model. RF and two different pulsed I-V techniques were initially applied to partially
depleted silicon-on-insulator (PDSOI) devices. The pulsed I-V hot chuck method
showed good agreement with the RF technique in the PDSOI devices. However,
subsequent analysis demonstrated that for more advanced technologies the time domain
methods can underestimate self-heating. This is due to the reduction of the thermal time
constants into the nanosecond range and limitations of the pulsed I-V set-up. The
reduction is related to the major increase of the surface to volume ratio in advanced
MOSFETs. Consequently the work showed that the thermal properties of advanced
semiconductor devices must be characterised within the frequency domain.
For UTBB devices with 7-8 nm Si body and 10 nm ultra-thin buried oxide (BOX)
the analogue performance degradation caused by the substrate effects can be stronger
than the analogue performance degradation caused by self-heating. However, the
substrate effects can be effectively reduced if the substrate doping beneath the buried
ii
oxide is adjusted using a ground plane. In the MHz – GHz frequency range the intrinsic
voltage gain variation is reduced ~6 times when a device is biased in saturation if a
ground plane is implemented compared with a device without a ground plane.
UTBB devices with 25 nm BOX were compared with UTBB devices with 10 nm
BOX. It was found that the buried oxide thinning from 25 nm to 10 nm is not critical
from the thermal point of view as other heat evacuation paths (e.g. source and drain)
start to play a role.
Thermal and substrate effects in FinFETs were also analysed. It was experimentally
shown that FinFET thermal properties depend on the device geometry. The thermal
resistance of FinFETs strongly varies with the fin width and number of parallel fins,
whereas the fin spacing is less critical. The results suggest that there are trade-offs
between thermal properties and integration density, electrostatic control and design
complexity, since these aspects depend on device geometry. The high frequency
substrate effects were found to be effectively reduced in devices with sub-100 nm wide
fins.Engineering and Physical Sciences Research Council
(EPSRC) and EU fundin