A hierarchical architecture for increasing efficiency of large photovoltaic plants under non-homogeneous solar irradiation

Under non-homogeneous solar irradiation, photovoltaic (PV) panels receive different solar irradiance, resulting in a decrease in efficiency of the PV generation system. There are a few technical options to fix this issue that goes under the name of mismatch. One of these is the reconfiguration of the PV generation system, namely changing the connections of the PV panels from the initial configuration to the optimal one. Such technique has been widely considered for small systems, due to the excessive number of required switches. In this paper, the authors propose a new method for increasing the efficiency of large PV systems under non-homogeneous solar irradiation using Series-Parallel (SP) topology. In the first part of the paper, the authors propose a method containing two key points: a switching matrix to change the connection of PV panels based on SP topology and the proof that the SP-based reconfiguration method can increase the efficiency of the photovoltaic system up to 50%. In the second part, the authors propose the extension of the method proposed in the first part to improve the efficiency of large solar generation systems by means of a two-levels architecture to minimize the cost of fabrication of the switching matrix

Reliability analysis of distribution systems with photovoltaic generation using a power flow simulator and a parallel Monte Carlo approach

This paper presents a Monte Carlo approach for reliability assessment of distribution systems with distributed generation using parallel computing. The calculations are carried out with a royalty-free power flow simulator, OpenDSS (Open Distribution System Simulator). The procedure has been implemented in an environment in which OpenDSS is driven from MATLAB. The test system is an overhead distribution system represented by means of a three-phase model that includes protective devices. The paper details the implemented procedure, which can be applied to systems with or without distributed generation, includes an illustrative case study and summarizes the results derived from the analysis of the test system during one year. The goal is to evaluate the test system performance considering different scenarios with different level of system automation and reconfiguration, and assess the impact that distributed photovoltaic generation can have on that performance. Several reliability indices, including those related to the impact of distributed generation, are obtained for every scenario.Postprint (published version

Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM based FPGA

Efficient low complexity error correcting code(ECC) is considered as an effective technique for mitigation of multi-bit upset (MBU) in the configuration memory(CM)of static random access memory (SRAM) based Field Programmable Gate Array (FPGA) devices. Traditional multi-bit ECCs have large overhead and complex decoding circuit to correct adjacent multibit error. In this work, we propose a simple multi-bit ECC which uses Secure Hash Algorithm for error detection and parity based two dimensional Erasure Product Code for error correction. Present error mitigation techniques perform error correction in the CM without considering the criticality or the execution period of the tasks allocated in different portion of CM. In most of the cases, error correction is not done in the right instant, which sometimes either suspends normal system operation or wastes hardware resources for less critical tasks. In this paper,we advocate for a dynamic priority-based hardware scheduling algorithm which chooses the tasks for error correction based on their area, execution period and criticality. The proposed method has been validated in terms of overhead due to redundant bits, error correction time and system reliabilityComment: 6 pages, 8 figures, conferenc

Coarse-grained reconfigurable array architectures

Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures. By executing non-loop code on other cores, however, CGRAs can focus on such loops to execute them more efficiently. This chapter discusses the basic principles of CGRAs, and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs. The impact of different options on flexibility, performance, and power-efficiency is discussed, as well as the need for compiler support. The ADRES CGRA design template is studied in more detail as a use case to illustrate the need for design space exploration, for compiler support and for the manual fine-tuning of source code