Combined Crosstalk Avoidance Code with Error Control Code for Detection and Correction of Random and Burst Errors

Error correction codes are majorly important to detect and correct occurred errors because of various noise sources. When the technology is scaling down, the effect of noise sources is high. The coupling capacitance is one of the main constraints to affect the performance of on-chip interconnects. Because of coupling capacitance, the crosstalk is introduced at on-chip interconnecting wires. To control the single or multiple errors, an efficient error correction code is required. By combining crosstalk avoidance with error control code, the reliable intercommunication is obtained in network-on-chip (NoC)-based system on chip (SoC). To reduce the power consumption of error control codes, the bus invert-based low-power code is integrated to network interface of NoC. The advanced work is designed and implemented with Xilinx 14.7; thereby the performance of improved NoC is evaluated and compared with existing work. The 8×8 mesh-based NoC is simulated at various traffic patterns to analyze the energy dissipation and average data packet latency

Book Review

A Scholarly Review of “Error Control for Network-On-Chip Links” (Authors: Bo Fu and Paul Ampadu, 2012)Fu, B.; and Ampadu, P. 2012. Error Control for Network-On-Chip Links.Springer Science+Business Media, LLC, New York, NY, USA.Available: <http://dx.doi.org/10.1007/978-1-4419-9313-7>

Communication Reliability in Network on Chip Designs

The performance of low latency Network on Chip (NoC) architectures, which incorporate fast bypass paths to reduce communication latency, is limited by crosstalk induced skewing of signal transitions on link wires. As a result of crosstalk interactions between wires, signal transitions belonging to the same flit or bit vector arrive at the destination at different times and are likely to violate setup and hold time constraints for the design. This thesis proposes a two-step technique: TransSync- RecSync, to dynamically eliminate packet errors resulting from inter-bit-line transition skew. The proposed approach adds minimally to router complexity and involves no wire overhead. The actual throughput of NoC designs with asynchronous bypass designs is evaluated and the benefits of augmenting such schemes with the proposed design are studied. The TransSync, TransSync-2-lines and RecSync schemes described here are found to improve the average communication latency by 26%, 20% and 38% respectively in a 7X7 mesh NoC with asynchronous bypass channel. This work also evaluates the bit-error ratio (BER) performance of several existing crosstalk avoidance and error correcting schemes and compares them to that of the proposed schemes. Both TransSync and RecSync scheme are dynamic in nature and can be switched on and off on-the-fly. The proposed schemes can therefore be employed to impart unequal error protection (UEP) against intra-flit skewing on NoC links. In the UEP, a larger fraction of the energy budget is spent in providing protection to those parts of the data being transmitted on the link which have a higher priority, while expending smaller effort in protecting relatively less important parts of the data. This allows us to achieve the prescribed level of performance with lower levels of power. The benefits of the presented technique are illustrated using an H.264 video decoder system-on-chip (SoC) employing NoC architecture. We show that for Akyio test streams transmitted over 3mm long link wires, the power consumption can be reduced by as much as 20% at the cost of an acceptable degradation in average peak signal to noise ratio (PSNR) with UEP

Split-enabled 350–630 Gb/s optical interconnect with direct detection NOMA-CAP and 7-core multi-core fiber

The ever-growing data traffic volume inside data centers caused by the popularization of cloud services and edge computing demands scalable and cost-efficient network infrastructures. With this premise, optical interconnects have recently gained more and more research attention as a key building block to ensure end-to-end energy efficient solutions, offering high throughput, low latency and reduced energy consumption compared to current networks based on active optical cables. An efficient way for performing such optical interconnects is to make use of multi-core fibers (MCFs), which enables the multiplexing of several spatial channels, each using a different core inside the same fiber cladding. Moreover, non-orthogonal multiple access combined with multi-band carrierless amplitude and phase modulation (NOMA-CAP) has been recently proposed as a potential candidate to increase the network capacity and an efficiency/flexibility resource management. In this paper, using direct detection we experimentally demonstrate the transmission of NOMA-CAP signals through a 2 km MCF with 7 spatial channels for high capacity optical interconnect applications. The results show negligible transmission penalty for different total aggregated traffics ranging from 350 Gb/s to 630 Gb/s.This work was supported in part by ALLIANCE (TEC2017-90034-C2-2-R) project co-funded by FEDER, the European Union’s Horizon 2020 research and innovation programme under grant agreement no780997 (plaCMOS), as well as MINECO FPI-BES-2015-074302Peer ReviewedPostprint (author's final draft