A 10b SAR ADC with an Ultra-Low Power Supply

A 0.2V 10-bit 5 kS/s Successive Approximation Register ADC design is presented. This design achieves a very low power consumption due to the ultra-low power supply voltage used. Different aspects in the ADC design are optimized for 0.2V and modified to meet the speed requirements for the ADC. Preliminary Cadence simulations show a 4nW total power consumption with a peak SNDR of 57 dB and a FOM of 1.3 fJ/conversion-step

A 10-bit SAR ADC with an Ultra-Low Power Supply

This paper presents a successive approximation analog-to-digital converter (SAR ADC) design, which operates with a 0.2 V power supply. The design utilizes a dynamic bulk biasing scheme to dynamically adjust the relative NMOS and PMOS strengths, which are very sensitive to temperature, process, and mismatch variations at low supply voltages. The design achieves a very low power consumption due to the 0.2 V supply. Several circuits in the design are optimized for full functionality at 0.2 V. Extracted simulations show a total power consumption of 9 nW with a peak SNDR of 61.3 dB and a Walden Figure of Merit of 1.91 fJ/conversion-step

Ultra-Low Power ADCs for Space Sensors and Instruments

A 28nm 0.1V 10-bit 2kS/s Successive Approximation Register ADC design is proposed. This design opens the doors to both low supply and low power space sensors and instruments. Due to the stringent voltage supply unique challenges arise that are met with innovation in the sample switch and comparator design. These components of the ADC architecture are optimized to perform successfully at a 0.1V supply with a sample rate suitable for most sensor applications

A Charge-Recycling Scheme and Ultra Low Voltage Self-Startup Charge Pump for Highly Energy Efficient Mixed Signal Systems-On-A-Chip

The advent of battery operated sensor-based electronic systems has provided a pressing need to design energy-efficient, ultra-low power integrated circuits as a means to improve the battery lifetime. This dissertation describes a scheme to lower the power requirement of a digital circuit through the use of charge-recycling and dynamic supply-voltage scaling techniques. The novel charge-recycling scheme proposed in this research demonstrates the feasibility of operating digital circuits using the charge scavenged from the leakage and dynamic load currents inherent to digital design. The proposed scheme efficiently gathers the “ground-bound” charge into storage capacitor banks. This reclaimed charge is then subsequently recycled to power the source digital circuit. The charge-recycling methodology has been implemented on a 12-bit Gray-code counter operating at frequencies of less than 50 MHz. The circuit has been designed in a 90-nm process and measurement results reveal more than 41% reduction in the average energy consumption of the counter. The total energy savings including the power consumed for the generation of control signals aggregates to an average of 23%. The proposed methodology can be applied to an existing digital path without any design change to the circuit but with only small loss to the performance. Potential applications of this scheme are described, specifically in wide-temperature dynamic power reduction and as a source for energy harvesters. The second part of this dissertation deals with the design and development of a self-starting, ultra-low voltage, switched-capacitor (SC) DC-DC converter that is essential to an energy harvesting system. The proposed charge-pump based SC-converter operates from 125-mV input and thus enables battery-less operation in ultra-low voltage energy harvesters. The charge pump does not require any external components or expensive post-fabrication processing to enable low-voltage operation. This design has been implemented in a 130-nm CMOS process. While the proposed charge pump provides significant efficiency enhancement in energy harvesters, it can also be incorporated within charge recycling systems to facilitate adaptable charge-recycling levels. In total, this dissertation provides key components needed for highly energy-efficient mixed signal systems-on-a-chip

Ultra-Low Power ADCs for Space Sensors and Instruments

A 28nm 0.1V 10-bit 2kS/s time domain ADC design is proposed. This design opens the doors to both low supply and low power space sensors and instruments. Due to the stringent voltage supply, unique challenges arise that are met with innovation in the sample switch and the quantizer design. These components of the ADC architecture are optimized to perform successfully at a 0.1V supply with a sample rate suitable for most sensor applications

A 10-bit Charge-Redistribution ADC Consuming 1.9 μW at 1 MS/s

This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115--225 μm2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 μW and achieves an energy efficiency of 4.4 fJ/conversion-step

Complementary tunnel gate topology to reduce crosstalk effects

Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome power density and energy inefficiency exhibited by CMOS technology. There are design challenges associated to their distinguishing characteristic which are being addressed. In this paper the impact of the non-symmetric conduction of tunnel transistors (TFETs) on the speed of TFETs circuits under crosstalk is analyzed and a novel topology for complementary tunnel transistors gates, which mitigates the observed performance degradation without power penalties, is described and evaluated

A 28 nm 368 fJ/cycle, 0.43%/V Supply Sensitivity, FLL based RC Oscillator Featuring Positive TC Only Resistors and ΣM Based Trimming

This Brief presents a process-scaling-friendly frequency-locked-loop (FLL)-based RC oscillator. It features an R-R-C frequency-to-voltage converter that entails resistors with only the same-sign temperature coefficients. Together with a low-leakage switched-capacitor resistor and a delta-sigma-modulator-based trimming, our 71.8-MHz RC oscillator in 28-nm CMOS achieves a frequency inaccuracy of 77.6 ppm/0C, a 0.43%/V supply sensitivity, and an 11-psrms period jitter. The energy efficiency is 368 fJ/cycle

Advanced modelling and design considerations for interconnects in ultra- low power digital system

PhD ThesisAs Very Large Scale Integration (VLSI) is progressing in very Deep submicron (DSM) regime without decreasing chip area, the importance of global interconnects increases but at the cost of performance and power consumption for advanced System-on- Chip (SoC)s. However, the growing complexity of interconnects behaviour presents a challenge for their adequate modelling, whereby conventional circuit theoretic approaches cannot provide sufficient accuracy. During the last decades, fractional differential calculus has been successfully applied to modelling certain classes of dynamical systems while keeping complexity of the models under acceptable bounds. For example, fractional calculus can help capturing inherent physical effects in electrical networks in a compact form, without following conventional assumptions about linearization of non-linear interconnect components. This thesis tackles the problem of interconnect modelling in its generality to simulate a wide range of interconnection configurations, its capacity to emulate irregular circuit elements and its simplicity in the form of responsible approximation. This includes modelling and analysing interconnections considering their irregular components to add more flexibility and freedom for design. The aim is to achieve the simplest adaptable model with the highest possible accuracy. Thus, the proposed model can be used for fast computer simulation of interconnection behaviour. In addition, this thesis proposes a low power circuit for driving a global interconnect at voltages close to the noise level. As a result, the proposed circuit demonstrates a promising solution to address the energy and performance issues related to scaling effects on interconnects along with soft errors that can be caused by neutron particles. The major contributions of this thesis are twofold. Firstly, in order to address Ultra-Low Power (ULP) design limitations, a novel driver scheme has been configured. This scheme uses a bootstrap circuitry which boosts the driver’s ability to drive a long interconnect with an important feedback feature in it. Hence, this approach achieves two objectives: improving performance and mitigating power consumption. Those achievements are essential in designing ULP circuits along with occupying a smaller footprint and being immune to noise, observed in this design as well. These have been verified by comparing the proposed design to the previous and traditional circuits using a simulation tool. Additionally, the boosting based approach has been shown beneficial in mitigating the effects of single event upset (SEU)s, which are known to affect DSM circuits working under low voltages. Secondly, the CMOS circuit driving a distributed RLC load has been brought in its analysis into the fractional order domain. This model will make the on-chip interconnect structure easy to adjust by including the effect of fractional orders on the interconnect timing, which has not been considered before. A second-order model for the transfer functions of the proposed general structure is derived, keeping the complexity associated with second-order models for this class of circuits at a minimum. The approach here attaches an important trait of robustness to the circuit design procedure; namely, by simply adjusting the fractional order we can avoid modifying the circuit components. This can also be used to optimise the estimation of the system’s delay for a broad range of frequencies, particularly at the beginning of the design flow, when computational speed is of paramount importance.Iraqi Ministry of Higher Education and Scientific Researc

Insights into tunnel FET-based charge pumps and rectifiers for energy harvesting applications

In this paper, the electrical characteristics of tunnel field-effect transistor (TFET) devices are explored for energy harvesting front-end circuits with ultralow power consumption. Compared with conventional thermionic technologies, the improved electrical characteristics of TFET devices are expected to increase the power conversion efficiency of front-end charge pumps and rectifiers powered at sub-µW power levels. However, under reverse bias conditions the TFET device presents particular electrical characteristics due to its different carrier injection mechanism. In this paper, it is shown that reverse losses in TFET-based circuits can be attenuated by changing the gate-to-source voltage of reverse-biased TFETs. Therefore, in order to take full advantage of the TFETs in front-end energy harvesting circuits, different circuit approaches are required. In this paper, we propose and discuss different topologies for TFET-based charge pumps and rectifiers for energy harvesting applications.Peer ReviewedPostprint (author's final draft