1,908 research outputs found
A Sound and Complete Axiomatization of Majority-n Logic
Manipulating logic functions via majority operators recently drew the
attention of researchers in computer science. For example, circuit optimization
based on majority operators enables superior results as compared to traditional
logic systems. Also, the Boolean satisfiability problem finds new solving
approaches when described in terms of majority decisions. To support computer
logic applications based on majority a sound and complete set of axioms is
required. Most of the recent advances in majority logic deal only with ternary
majority (MAJ- 3) operators because the axiomatization with solely MAJ-3 and
complementation operators is well understood. However, it is of interest
extending such axiomatization to n-ary majority operators (MAJ-n) from both the
theoretical and practical perspective. In this work, we address this issue by
introducing a sound and complete axiomatization of MAJ-n logic. Our
axiomatization naturally includes existing majority logic systems. Based on
this general set of axioms, computer applications can now fully exploit the
expressive power of majority logic.Comment: Accepted by the IEEE Transactions on Computer
Synthesis and Optimization of Reversible Circuits - A Survey
Reversible logic circuits have been historically motivated by theoretical
research in low-power electronics as well as practical improvement of
bit-manipulation transforms in cryptography and computer graphics. Recently,
reversible circuits have attracted interest as components of quantum
algorithms, as well as in photonic and nano-computing technologies where some
switching devices offer no signal gain. Research in generating reversible logic
distinguishes between circuit synthesis, post-synthesis optimization, and
technology mapping. In this survey, we review algorithmic paradigms ---
search-based, cycle-based, transformation-based, and BDD-based --- as well as
specific algorithms for reversible synthesis, both exact and heuristic. We
conclude the survey by outlining key open challenges in synthesis of reversible
and quantum logic, as well as most common misconceptions.Comment: 34 pages, 15 figures, 2 table
On reliable computation over larger alphabets
We present two new positive results for reliable computation using formulas
over physical alphabets of size . First, we show that for logical
alphabets of size the threshold for denoising using gates subject to
-ary symmetric noise with error probability is strictly larger
that possible for Boolean computation and we demonstrate a clone of -ary
functions that can be reliably computed up to this threshold. Secondly, we
provide an example where , showing that reliable Boolean computation
can be performed using -input ternary logic gates subject to symmetric
ternary noise of strength by using the additional alphabet
element for error signalling.Comment: 14 pages, 2 figure
Energy-Efficient Digital Circuit Design using Threshold Logic Gates
abstract: Improving energy efficiency has always been the prime objective of the custom and automated digital circuit design techniques. As a result, a multitude of methods to reduce power without sacrificing performance have been proposed. However, as the field of design automation has matured over the last few decades, there have been no new automated design techniques, that can provide considerable improvements in circuit power, leakage and area. Although emerging nano-devices are expected to replace the existing MOSFET devices, they are far from being as mature as semiconductor devices and their full potential and promises are many years away from being practical.
The research described in this dissertation consists of four main parts. First is a new circuit architecture of a differential threshold logic flipflop called PNAND. The PNAND gate is an edge-triggered multi-input sequential cell whose next state function is a threshold function of its inputs. Second a new approach, called hybridization, that replaces flipflops and parts of their logic cones with PNAND cells is described. The resulting \hybrid circuit, which consists of conventional logic cells and PNANDs, is shown to have significantly less power consumption, smaller area, less standby power and less power variation.
Third, a new architecture of a field programmable array, called field programmable threshold logic array (FPTLA), in which the standard lookup table (LUT) is replaced by a PNAND is described. The FPTLA is shown to have as much as 50% lower energy-delay product compared to conventional FPGA using well known FPGA modeling tool called VPR.
Fourth, a novel clock skewing technique that makes use of the completion detection feature of the differential mode flipflops is described. This clock skewing method improves the area and power of the ASIC circuits by increasing slack on timing paths. An additional advantage of this method is the elimination of hold time violation on given short paths.
Several circuit design methodologies such as retiming and asynchronous circuit design can use the proposed threshold logic gate effectively. Therefore, the use of threshold logic flipflops in conventional design methodologies opens new avenues of research towards more energy-efficient circuits.Dissertation/ThesisDoctoral Dissertation Computer Science 201
SYNTHESIS OF COMPOSITE LOGIC GATE IN QCA EMBEDDING UNDERLYING REGULAR CLOCKING
Quantum-dot Cellular Automata (QCA) has emerged as one of the alternative technologies for current CMOS technology. It has the advantage of computing at a faster speed, consuming lower power, and work at Nano- Scale. Besides these advantages, QCA logic is limited to its primitive gates, majority voter and inverter only, results in limitation of cost-efficient logic circuit realization. Numerous designs have been proposed to realize various intricate logic gates in QCA at the penalty of non-uniform clocking and improper layout. This paper proposes a Composite Gate (CG) in QCA, which realizes all the essential digital logic gates such as AND, NAND, Inverter, OR, NOR, and exclusive gates like XOR and XNOR. Reportedly, the proposed design is the first of its kind to generate all basic logic in a single unit. The most striking feature of this work is the augmentation of the underlying clocking circuit with the logic block, making it a more realistic circuit. The Reliable, Efficient, and Scalable (RES) underlying regular clocking scheme is utilized to enhance the proposed design’s scalability and efficiency. The relevance of the proposed design is best cited with coplanar implementation of 2-input symmetric functions, achieving 33% gain in gate count and without any garbage output. The evaluation and analysis of dissipated energy for both the design have been carried out. The end product is verified using the QCADesigner2.0.3 simulator, and QCAPro is employed for the study of power dissipation
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