Passive und aktive Radio Frequency Identification Tags im 60-GHz-Band

Die Einführung des millimeter-Wellen-Bandes eröffnet neue Perspektiven für die Radio Frequency Identification (RFID) Kommunikationssysteme. Der Enwurf des Systems im 60-GHz-Band ermöglicht die Implementierung der On-Chip Antenne und darüber hinaus die Implementierung eines RFID-Tags auf einem einzigen Chip. Dennoch ist es aufgrund der gesetzlichen Beschränkung der effektiven isotropen Strahlungsleistung (EIRP) des Lesegeräts und der erhöhten Freiraum-Dielektrikumsverluste eine Herausforderung, eine zuverlässige Kommunikationsreichweite von mehreren Millimetern zu erreichen. Neue Lösungen sind für jeden Block sowohl im Lesegerät als auch im Single-Chip-Tag erforderlich. Obwohl das Lesegerät batteriebetrieben ist, ist es immer noch eine Herausforderung, die maximal zulässigen 20 dBm IERP des Lesersenders energieeffizient zu erzeugen. Darüber hinaus sollte der Empfänger einen ausreichenden Dynamikbereich haben, um das vom Tag kommende Signal zu erkennen. Auf der Tag-Seite sind die Hauptherausforderungen das Co-Design der effizienten On-Chip-Antennen-Implementierung, die hochempfindliche Gleichrichter-Implementierung und das Rückkommunikationskonzept. Diese Arbeit konzentriert sich auf die Machbarkeitsstudie des Single-Chip-RFID-Tags und die Implementierung im Millimeterwellenbereich. Es werden zwei Rückkommunikationskonzepte untersucht - Backscattering-Rückkommunikation und eine Kommunikation unter Verwendung von Ultra-Low-Power (ULP) Radios. Beide werden in einem 22 nm FDSOI Prozess auf einem Substrat mit geringem Widerstand implementiert. Beide Tags arbeiten mit einer Versorgungsspannung von 0,4 V, um die Kommunikationsreichweite zu maximieren. Die Link-Budgets sind so ausgelegt, dass sie die regulatorischen Beschränkungen einhalten. Die Auswahl des Technologieknotens wird begründet. Verschiedene Aspekte im Zusammenhang mit der Technologie werden diskutiert, wie z. B. Geräteleistung, passiver Qualitätsfaktor, Leistungsdichte der Kondensatoren. Der Backscattering RFID-Tag wird zuerst entworfen, da er eine relativ einfachere Topologie hat. Die Probleme der Gleichrichterempfindlichkeit im Rahmen des analogen Frontends, der On-Chip-Antenneneffizienz und der konjugierten Anpassung beider werden untersucht. Eine Kommunikationsreichweite von 5 mm wird angestrebt und realisiert. Um die Kommunikationsreichweite weiter zu erhöhen, wird in der zweiten Phase ein Tag mit einer aktiven Rückkommunikation implementiert. Hier wird die Gleichrichterempfindlichkeit weiter verbessert. Es wird ein 0,4V ULP Radio entworfen, das sich die Antenne mit dem Gleichrichter über einen Single-Pole- Double-Through (SPDT) Schalter teilt. Ein Abstand von 2 cm erwies sich als realisierbar, wobei die gesetzlichen Bestimmungen eingehalten und der dynamische Bereich des Leseempfängers nicht überschritten wurde. Es wird die höchste normalisierte Kommunikationsreichweite pro Leser-EIRP erreicht. Weitere Verbesserungsmöglichkeiten werden diskutiert

Energy-Efficient Wireless Connectivity and Wireless Charging For Internet-of-Things (IoT) Applications

During the recent years, the Internet-of-Things (IoT) has been rapidly evolving. It is indeed the future of communication that has transformed Things of the real world into smarter devices. To date, the world has deployed billions of “smart” connected things. Predictions say there will be 10’s of billions of connected devices by 2025 and in our lifetime we will experience life with a trillion-node network. However, battery lifespan exhibits a critical barrier to scaling IoT devices. Replacing batteries on a trillion-sensor scale is a logistically prohibitive feat. Self-powered IoT devices seems to be the right direction to stand up to that challenge. The main objective of this thesis is to develop solutions to achieve energy-efficient wireless-connectivity and wireless-charging for IoT applications. In the first part of the thesis, I introduce ultra-low power radios that are compatible with the Bluetooth Low-Energy (BLE) standard. BLE is considered as the preeminent protocol for short-range communications that support transmission ranges up to 10’s of meters. Number of low power BLE transmitter (TX) and receiver (RX) architectures have been designed, fabricated and tested in different planar CMOS and FinFET technologies. The low power operation is achieved by combining low power techniques in both the network and physical layers, namely: backchannel communication, duty-cycling, open-loop transmission/reception, PLL-less architectures, and mixer-first architectures. Further novel techniques have been proposed to further reduce the power the consumption of the radio design, including: a fast startup time and low startup energy crystal oscillators, an antenna-chip co-design approach for quadrature generation in the RF path, an ultra-low power discrete-time differentiator-based Gaussian Frequency Shift Keying (GFSK) demodulation scheme, an oversampling GFSK modulation/demodulation scheme for open loop transmission/reception and packet synchronization, and a cell-based design approach that allows automation in the design of BLE digital architectures. The implemented BLE TXs transmit fully-compliant BLE advertising packet that can be received by commercial smartphone. In the second part of the thesis, I introduce passive nonlinear resonant circuits to achieve wide-band RF energy harvesting and robust wireless power transfer circuits. Nonlinear resonant circuits modeled by the Duffing nonlinear differential equation exhibit interesting hysteresis characteristics in their frequency and amplitude responses that are exploited in designing self-adaptive wireless charging systems. In the magnetic-resonance wireless power transfer scenario, coupled nonlinear resonators are proposed to maintain the power transfer level and efficiency over a range of coupling factors without active feedback control circuitry. Coupling factor depends on the transmission distance, lateral, and angular misalignments between the charging pad and the device. Therefore, nonlinear resonance extends the efficient charging zones of a wireless charger without the requirement for a precise alignment.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/169842/1/omaratty_1.pd

Circuits and Systems for Energy Harvesting and Internet of Things Applications

The Internet of Things (IoT) continues its growing trend, while new “smart” objects are con-stantly being developed and commercialized in the market. Under this paradigm, every common object will be soon connected to the Internet: mobile and wearable devices, electric appliances, home electronics and even cars will have Internet connectivity. Not only that, but a variety of wireless sensors are being proposed for different consumer and industrial applications. With the possibility of having hundreds of billions of IoT objects deployed all around us in the coming years, the social implications and the economic impact of IoT technology needs to be seriously considered. There are still many challenges, however, awaiting a solution in order to realize this future vision of a connected world. A very important bottleneck is the limited lifetime of battery powered wireless devices. Fully depleted batteries need to be replaced, which in perspective would generate costly maintenance requirements and environmental pollution. However, a very plausible solution to this dilemma can be found in harvesting energy from the ambient. This dissertation focuses in the design of circuits and system for energy harvesting and Internet of Things applications. The first part of this dissertation introduces the research motivation and fundamentals of energy harvesting and power management units (PMUs). The architecture of IoT sensor nodes and PMUs is examined to observe the limitations of modern energy harvesting systems. Moreover, several architectures for multisource harvesting are reviewed, providing a background for the research presented here. Then, a new fully integrated system architecture for multisource energy harvesting is presented. The design methodology, implementation, trade-offs and measurement results of the proposed system are described. The second part of this dissertation focus on the design and implementation of low-power wireless sensor nodes for precision agriculture. First, a sensor node incorporating solar energy harvesting and a dynamic power management strategy is presented. The operation of a wireless sensor network for soil parameter estimation, consisting of four nodes is demonstrated. After that, a solar thermoelectric generator (STEG) prototype for powering a wireless sensor node is proposed. The implemented solar thermoelectric generator demonstrates to be an alternative way to harvest ambient energy, opening the possibility for its use in agricultural and environmental applications. The open problems in energy harvesting for IoT devices are discussed at the end, to delineate the possible future work to improve the performance of EH systems. For all the presented works, proof-of-concept prototypes were fabricated and tested. The measured results are used to verify their correct operation and performance

Wireless wire - ultra-low-power and high-data-rate wireless communication systems

With the rapid development of communication technologies, wireless personal-area communication systems gain momentum and become increasingly important. When the market gets gradually saturated and the technology becomes much more mature, new demands on higher throughput push the wireless communication further into the high-frequency and high-data-rate direction. For example, in the IEEE 802.15.3c standard, a 60-GHz physical layer is specified, which occupies the unlicensed 57 to 64 GHz band and supports gigabit links for applications such as wireless downloading and data streaming. Along with the progress, however, both wireless protocols and physical systems and devices start to become very complex. Due to the limited cut-off frequency of the technology and high parasitic and noise levels at high frequency bands, the power consumption of these systems, especially of the RF front-ends, increases significantly. The reason behind this is that RF performance does not scale with technology at the same rate as digital baseband circuits. Based on the challenges encountered, the wireless-wire system is proposed for the millimeter wave high-data-rate communication. In this system, beamsteering directional communication front-ends are used, which confine the RF power within a narrow beam and increase the level of the equivalent isotropic radiation power by a factor equal to the number of antenna elements. Since extra gain is obtained from the antenna beamsteering, less front-end gain is required, which will reduce the power consumption accordingly. Besides, the narrow beam also reduces the interference level to other nodes. In order to minimize the system average power consumption, an ultra-low power asynchronous duty-cycled wake-up receiver is added to listen to the channel and control the communication modes. The main receiver is switched on by the wake-up receiver only when the communication is identified while in other cases it will always be in sleep mode with virtually no power consumed. Before transmitting the payload, the event-triggered transmitter will send a wake-up beacon to the wake-up receiver. As long as the wake-up beacon is longer than one cycle of the wake-up receiver, it can be captured and identified. Furthermore, by adopting a frequency-sweeping injection locking oscillator, the wake-up receiver is able to achieve good sensitivity, low latency and wide bandwidth simultaneously. In this way, high-data-rate communication can be achieved with ultra-low average power consumption. System power optimization is achieved by optimizing the antenna number, data rate, modulation scheme, transceiver architecture, and transceiver circuitries with regards to particular application scenarios. Cross-layer power optimization is performed as well. In order to verify the most critical elements of this new approach, a W-band injection-locked oscillator and the wake-up receiver have been designed and implemented in standard TSMC 65-nm CMOS technology. It can be seen from the measurement results that the wake-up receiver is able to achieve about -60 dBm sensitivity, 10 mW peak power consumption and 8.5 µs worst-case latency simultaneously. When applying a duty-cycling scheme, the average power of the wake-up receiver becomes lower than 10 µW if the event frequency is 1000 times/day, which matches battery-based or energy harvesting-based wireless applications. A 4-path phased-array main receiver is simulated working with 1 Gbps data rate and on-off-keying modulation. The average power consumption is 10 µW with 10 Gb communication data per day

Designing Novel Hardware Security Primitives for Smart Computing Devices

Smart computing devices are miniaturized electronics devices that can sense their surroundings, communicate, and share information autonomously with other devices to work cohesively. Smart devices have played a major role in improving quality of the life and boosting the global economy. They are ubiquitously present, smart home, smart city, smart girds, industry, healthcare, controlling the hazardous environment, and military, etc. However, we have witnessed an exponential rise in potential threat vectors and physical attacks in recent years. The conventional software-based security approaches are not suitable in the smart computing device, therefore, hardware-enabled security solutions have emerged as an attractive choice. Developing hardware security primitives, such as True Random Number Generator (TRNG) and Physically Unclonable Function (PUF) from electrical properties of the sensor could be a novel research direction. Secondly, the Lightweight Cryptographic (LWC) ciphers used in smart computing devices are found vulnerable against Correlation Power Analysis (CPA) attack. The CPA performs statistical analysis of the power consumption of the cryptographic core and reveals the encryption key. The countermeasure against CPA results in an increase in energy consumption, therefore, they are not suitable for battery operated smart computing devices. The primary goal of this dissertation is to develop novel hardware security primitives from existing sensors and energy-efficient LWC circuit implementation with CPA resilience. To achieve these. we focus on developing TRNG and PUF from existing photoresistor and photovoltaic solar cell sensors in smart devices Further, we explored energy recovery computing (also known as adiabatic computing) circuit design technique that reduces the energy consumption compared to baseline CMOS logic design and same time increasing CPA resilience in low-frequency applications, e.g. wearable fitness gadgets, hearing aid and biomedical instruments. The first contribution of this dissertation is to develop a TRNG prototype from the uncertainty present in photoresistor sensors. The existing sensor-based TRNGs suffer a low random bit generation rate, therefore, are not suitable in real-time applications. The proposed prototype has an average random bit generation rate of 8 kbps, 32 times higher than the existing sensor-based TRNG. The proposed lightweight scrambling method results in random bit entropy close to ideal value 1. The proposed TRNG prototype passes all 15 statistical tests of the National Institute of Standards and Technology (NIST) Statistical Test Suite with quality performance. The second contribution of this dissertation is to develop an integrated TRNG-PUF designed using photovoltaic solar cell sensors. The TRNG and PUF are mutually independent in the way they are designed, therefore, integrating them as one architecture can be beneficial in resource-constrained computing devices. We propose a novel histogram-based technique to segregate photovoltaic solar cell sensor response suitable for TRNG and PUF respectively. The proposed prototype archives approximately 34\% improvement in TRNG output. The proposed prototype achieves an average of 92.13\% reliability and 50.91\% uniformity performance in PUF response. The proposed sensor-based hardware security primitives do not require additional interfacing hardware. Therefore, they can be ported as a software update on existing photoresistor and photovoltaic sensor-based devices. Furthermore, the sensor-based design approach can identify physically tempered and faulty sensor nodes during authentication as their response bit differs. The third contribution is towards the development of a novel 2-phase sinusoidal clocking implementation, 2-SPGAL for existing Symmetric Pass Gate Adiabatic Logic (SPGAL). The proposed 2-SPGAL logic-based LWC cipher PRESENT shows an average of 49.34\% energy saving compared to baseline CMOS logic implementation. Furthermore, the 2-SPGAL prototype has an average of 22.76\% better energy saving compared to 2-EE-SPFAL (2-phase Energy-Efficient-Secure Positive Feedback Adiabatic Logic). The proposed 2-SPGAL was tested for energy-efficiency performance for the frequency range of 50 kHz to 250 kHz, used in healthcare gadgets and biomedical instruments. The proposed 2-SPGAL based design saves 16.78\% transistor count compared to 2-EE-SPFAL counterpart. The final contribution is to explore Clocked CMOS Adiabatic Logic (CCAL) to design a cryptographic circuit. Previously proposed 2-SPGAL and 2-EE-SPFAL uses two complementary pairs of the transistor evaluation network, thus resulting in a higher transistor count compared to the CMOS counterpart. The CCAL structure is very similar to CMOS and unlike 2-SPGAL and 2-EE-SPFAL, it does not require discharge circuitry to improve security performance. The case-study implementation LWC cipher PRESENT S-Box using CCAL results into 45.74\% and 34.88\% transistor count saving compared to 2-EE-SPFAL and 2-SPGAL counterpart. Furthermore, the case-study implementation using CCAL shows more than 95\% energy saving compared to CMOS logic at frequency range 50 kHz to 125 kHz, and approximately 60\% energy saving at frequency 250 kHz. The case study also shows 32.67\% and 11.21\% more energy saving compared to 2-EE-SPFAL and 2-SPGAL respectively at frequency 250 kHz. We also show that 200 fF of tank capacitor in the clock generator circuit results in optimum energy and security performance in CCAL

Energy autonomous systems : future trends in devices, technology, and systems

The rapid evolution of electronic devices since the beginning of the nanoelectronics era has brought about exceptional computational power in an ever shrinking system footprint. This has enabled among others the wealth of nomadic battery powered wireless systems (smart phones, mp3 players, GPS, …) that society currently enjoys. Emerging integration technologies enabling even smaller volumes and the associated increased functional density may bring about a new revolution in systems targeting wearable healthcare, wellness, lifestyle and industrial monitoring applications

Modelagem e projeto de conversores AC/DC de ultrabaixa tensão de operação

Tese (doutorado) - Universidade Federal de Santa Catarina, Centro Tecnológico. Programa de Pós-Graduação em Engenharia ElétricaEsta tese apresenta o desenvolvimento de um modelo analítico e muito simples do circuito retificador, considerando a lei corrente-tensão (exponencial) do diodo, tendo como mérito simplificar um problema relativamente complexo e não linear (retificador) com uma ótima precisão. O modelo mostra-se válido, mesmo para tensões abaixo da tensão térmica, tendo sido testado para um ampla variação de tensão e corrente. São apresentadas equações para a tensão DC de saída, ripple de tensão, transiente durante o startup e eficiência de conversão de potência. Para validação, o modelo é comparado à simulações realizadas em simulador SPICE e a resultados experimentais, mostrando uma ótima precisão. Comparando-se este modelo com outros citados nas referências bibliográficas, este possui a vantagem de ser analítico, mais simples e/ou mais preciso. O desenvolvimento deste modelo torna-se mais importante, à medida que cresce o interesse pela utilização de sensores remotos autoalimentados, e também pelo uso de dispositivos de identificação por rádiofrequência (RFID). O espaço de projeto do conversor AC/DC foi explorado por meio de equações simples e de uma metodologia de projeto desenvolvida para que, através de gráficos, o projetista possa de forma fácil, rápida e com boa precisão, determinar os principais elementos do conversor AC/DC e da rede de adaptação de impedâncias. Para alcançar potências menores na entrada do conversor AC/DC, a metodologia utiliza redes de adaptação de impedâncias para o casamento entre as impedâncias da antena (ou impedância da fonte geradora de sinal AC) e do conversor AC/DC. Além disso, esta metodologia pode ser utilizada para conversores AC/DC com diodos ou transistores conectados como diodos, mesmo que sua equação característica não seja a do diodo exponencial. Para a utilização do conversor AC/DC em circuitos integrados, são estudadas as possibilidades de uso do transistor MOS conectado como diodo operando na região de inversão fraca. Para obter suporte experimental, foram projetados multiplicadores de tensão, com rede de adaptação de impedâncias incorporada ao circuito integrado e também externa ao mesmo, com o objetivo de atingir a menor potência de entrada disponível.This thesis presents a simple analytical model of the rectifier circuit assuming that the diode is characterized by the exponential current-voltage law. The model shown is valid even for voltages below the thermal voltage and it has been tested for a wide range of voltages and currents. Equations are provided for the DC output voltage, ripple voltage, transient during startup and power conversion efficiency. For validation, the model is compared to simulations carried out in SPICE and experimental results, showing a good accuracy. Comparing this model with others cited in the references, this one has the advantage of being analytical, simpler, and more accurate. The development of this model becomes more relevant with the growing use of self powered remote sensors, and radio frequency identification devices (RFID). The design space of the AC/DC converter was explored using a graphic methodology. To operate with reduced power at the input, the methodology uses an impedance adaptation network for the matching between the impedances of the antenna (or the source impedance of the AC signal) and that of the AC/DC converter. Furthermore, this methodology can be used for AC/DC converters with diodes or transistors connected as diodes, even if their characteristic equations are not exponential. To obtain experimental support, voltage multipliers have been designed with impedance adaptation network incorporated into the integrated circuit and also external to it, in order to achieve the lowest possible power at the input

Sensor de temperatura integrado alimentado por RF

Dissertação (mestrado) - Universidade Federal de Santa Catarina, Centro Tecnológico, Programa de Pós-Graduação em Engenharia Elétrica, Florianópolis, 2013.Com o aumento do interesse na pesquisa em dispositivos eletrônicosinstalados no corpo humano, que se beneficiam de métodos nãoconvencionaisde captação de energia, o estudo e aprimoramento de taismétodos se torna necessário. Um desses métodos é a transferência de energiapor sinais eletromagnéticos de radiofrequência (RF). Tendo isso em vista,este trabalho apresenta o desenvolvimento de um sensor de temperaturaCMOS alimentado por RF aplicado na medição de temperatura do corpohumano. O sensor recebe energia via um sinal RF emitido por um dispositivoleitor. Uma vez que o sensor armazenou energia suficiente, eleenvia informação sobre a temperatura medida para o leitor. Para executartal função, os seguintes circuitos foram desenvolvidos: retificador, limitadorde tensão, fonte de referência, seletor de modo de operação, regulador detensão, oscilador e dispositivo de modulação de carga. Foi desenvolvidoum sistema que opera com um sinal RF de entrada com potência maior que-10dBm e frequência 900MHz, utilizando a tecnologia de fabricação IBM130nm. O sistema possui consumo de corrente igual a 8,5µA no modo ativoe 4,9µA no modo standby. Além disso, foi implementado um método decalibração do sensor, projetado para obter erro de medição de temperaturamenor que 0,2oC. Nesta dissertação, o projeto e simulação desses blocos sãodetalhados, bem como o teste de alguns blocos que foram fabricados. Abstract : With the increasing interest in research in biomedical electronic devices,which benefits from non-conventional energy transfer and harvestingmethods, the study and development of such methods becomes necessary.One of those methods is the wireless energy transfer. This work presents thedevelopment of a wirelessly powered CMOS temperature sensor, designedto measure temperatures in the human body temperature range. The sensorreceives energy through an RF signal emmited by a reader device. Once thesensor has enough energy, it sends data about the measured temperature tothe reader. The system was designed to operate with signal levels as low as-10dBm centered at 900MHz. The sensor device is formed by the followingcircuits: rectifier, voltage limiter, reference source, operating mode selector,voltage regulator, oscillator and backscattering device. The system presented8.5µA current comsumption in active mode and 4.9µA in standby mode.The developed sensor contains a calibration method, which was designed toachievemaximumtemperaturemeasurement error of 0.2oC. In this work, thedesign and simulation of these circuits are detailed, as well as the test of someblocks that were fabricated

Low power design of a versatile analog mixed Signal sensor module

The development of space electronics especially for launcher such as Ariane 6 has to fulfill space standards and space requirements provided by the space industries. The standards of the European Cooperation for Space Standardization (ECSS) are used extensively to ensure a development process that meets the space requirements. This standard covers space project management, space product assurance and space engineering. The ECSS is a cooperative effort of the European Space Agency, national Space Agencies and European Industry Associations for the purpose of developing and maintaining common standards. The work presented in this dissertation was carried out to fill the gap of developing wireless sensor network for Ariane launchers. The development process follows the space requirements that demand the sensor node to survive the environmental condition inside the launcher. This makes the work uniquely compared to commercial wireless sensor network development. The versatile analog mixed signal module proposed in this work consists of infrared transmitter, VLC receiver, power management, data processing with digital/analog sensor interface unit and solar cell as energy harvester. The sensor module is used to build wireless sensor network inside the Vehicle Equipment Bay (VEB) of Ariane 5

Ultra-Low-Power Uwb Impulse Radio Design: Architecture, Circuits, And Applications

Recent advances in home healthcare, environmental sensing, and low power computing have created a need for wireless communication at very low power for low data rate applications. Due to higher energy/bit requirements at lower data -rate, achieving power levels low enough to enable long battery lifetime (~10 years) or power-harvesting supplies have not been possible with traditional approaches. Dutycycled radios have often been proposed in literature as a solution for such applications due to their ability to shut off the static power consumption at low data rates. While earlier radio nodes for such systems have been proposed based on a type of sleepwake scheduling, such implementations are still power hungry due to large synchronization uncertainty (~1[MICRO SIGN]s). In this dissertation, we utilize impulsive signaling and a pulse-coupled oscillator (PCO) based synchronization scheme to facilitate a globally synchronized wireless network. We have modeled this network over a widely varying parameter space and found that it is capable of reducing system cost as well as providing scalability in wireless sensor networks. Based on this scheme, we implemented an FCC compliant, 3-5GHz, timemultiplexed, dual-band UWB impulse radio transceiver, measured to consume only 20[MICRO SIGN]W when the nodes are synchronized for peer-peer communication. At the system level the design was measured to consume 86[MICRO SIGN]W of power, while facilitating multi- hop communication. Simple pulse-shaping circuitry ensures spectral efficiency, FCC compliance and ~30dB band-isolation. Similarly, the band-switchable, ~2ns turn-on receiver implements a non-coherent pulse detection scheme that facilitates low power consumption with -87dBm sensitivity at 100Kbps. Once synchronized the nodes exchange information while duty-cycling, and can use any type of high level network protocols utilized in packet based communication. For robust network performance, a localized synchronization detection scheme based on relative timing and statistics of the PCO firing and the timing pulses ("sync") is reported. No active hand-shaking is required for nodes to detect synchronization. A self-reinforcement scheme also helps maintain synchronization even in the presence of miss-detections. Finally we discuss unique ways to exploit properties of pulse coupled oscillator networks to realize novel low power event communication, prioritization, localization and immediate neighborhood validation for low power wireless sensor applications