Building Programmable Wireless Networks: An Architectural Survey

In recent times, there have been a lot of efforts for improving the ossified Internet architecture in a bid to sustain unstinted growth and innovation. A major reason for the perceived architectural ossification is the lack of ability to program the network as a system. This situation has resulted partly from historical decisions in the original Internet design which emphasized decentralized network operations through co-located data and control planes on each network device. The situation for wireless networks is no different resulting in a lot of complexity and a plethora of largely incompatible wireless technologies. The emergence of "programmable wireless networks", that allow greater flexibility, ease of management and configurability, is a step in the right direction to overcome the aforementioned shortcomings of the wireless networks. In this paper, we provide a broad overview of the architectures proposed in literature for building programmable wireless networks focusing primarily on three popular techniques, i.e., software defined networks, cognitive radio networks, and virtualized networks. This survey is a self-contained tutorial on these techniques and its applications. We also discuss the opportunities and challenges in building next-generation programmable wireless networks and identify open research issues and future research directions.Comment: 19 page

A Programmable MAC Based System for Real-time and Non Real-time Flows in Wireless Networks

Wireless networks are increasingly being used to serve both real-time and non real-time flows. The former includes applications such as VoIP and video streaming, while the latter includes applications like file transfer and web browsing. These flows have very different service requirements. On the one hand, real-time flows usually require a strict per-packet delay bound, since late packets may not be useful to the application. On the other hand, non real-time flows do not pose any stringent delay requisites and only demand high throughput. Serving flows that have heterogeneous requirements necessitates the deployment of algorithms and rules for resource allocation that attempt to satisfy these needs. However, existing hardware does not allow such reconfigurability and is limited to providing a once-size-fits all solution. The objective of this work is to design, develop and demonstrate an architecture, specifically for software reconfigured hardware at the PHY-MAC layers that can provide such functionality at a per-flow and per-packet level, and to illustrate its superior performance to conventionally deployed solutions

Self-Adapting MAC Layer for Wireless Sensor Networks

The integration of wireless sensors with mobile phones is gaining momentum as an enabling platform for numerous emerging applications. These mobile systems face dynamic environments where both application requirements and ambient wireless conditions change frequently. Despite the existence of many MAC protocols however, none can provide optimal performance along multiple dimensions, in particular when the conditions are frequently changing. Instead of pursuing a one-MAC-fit all approach we present a Self-Adapting MAC Layer (SAML) comprising (1) a Reconfigurable MAC Architecture (RMA) that can switch to different MAC protocols at run time and (2) a learning-based MAC Selection Engine that selects the protocol most suitable for the current condition and requirements. As the ambient conditions or application requirements change SAML dynamically switches MAC protocols to gain the desired performance. To the application SAML appears as a traditional MAC protocol and its benefits are realized without troubling the application with the underlying complexity. To test the system we implement SAML in TinyOS 2.x and realize three prototypes containing up to five MACs. We evaluate the system in controlled tests and real-world environments using a new gateway device that integrates a 802.15.4 radio with Android phones. Our experimental results show that SAML provides an efficient and reliable MAC switching, while adheres to the application specified requirements

Decoupling User Interface Design Using Libraries of Reusable Components

The integration of electronic and mechanical hardware, software and interaction design presents a challenging design space for researchers developing physical user interfaces and interactive artifacts. Currently in the academic research community, physical user interfaces and interactive artifacts are predominantly designed and prototyped either as one-off instances from the ground up, or using functionally rich hardware toolkits and prototyping systems. During this prototyping phase, undertaking an integral design of the interface or interactive artifact’s electronic hardware is frequently constraining due to the tight couplings between the different design realms and the typical need for iterations as the design matures. Several current toolkit designs have consequently embraced component-sharing and component-swapping modular designs with a view to extending flexibility and improving researcher freedom by disentangling and softening the cause-effect couplings. Encouraged by early successes of these toolkits, this research work strives to further enhance these freedoms by pursuing an alternative style and dimension of hardware modularity. Another motivation is our goal to facilitate the design and development of certain classes of interfaces and interactive artifacts for which current electronic design approaches are argued to be restrictively constraining (e.g., relating to scale and complexity). Unfortunately, this goal of a new platform architecture is met with conceptual and technical challenges on the embedded system networking front. In response, this research investigates and extends a growing field of multi-module distributed embedded systems. We identify and characterize a sub-class of these systems, calling them embedded aggregates. We then outline and develop a framework for realizing the embedded aggregate class of systems. Toward this end, this thesis examines several architectures, topologies and communication protocols, making the case for and substantial steps toward the development of a suite of networking protocols and control algorithms to support embedded aggregates. We define a set of protocols, mechanisms and communication packets that collectively form the underlying framework for the aggregates. Following the aggregates design, we develop blades and tiles to support user interface researchers

A framework for the design, prototyping and evaluation of mobile interfaces for domestic environments

The idea of the smart home has been discussed for over three decades, but it has yet to achieve mass-market adoption. This thesis asks the question Why is my home not smart? It highlights four main areas that are barriers to adoption, and concentrates on a single one of these issues: usability. It presents an investigation that focuses on design, prototyping and evaluation of mobile interfaces for domestic environments resulting in the development of a novel framework. A smart home is the physical realisation of a ubiquitous computing system for domestic living. The research area offers numerous benefits to end-users such as convenience, assistive living, energy saving and improved security and safety. However, these benefits have yet to become accessible due to a lack of usable smart home control interfaces. This issue is considered a key reason for lack of adoption and is the focus for this thesis. Within this thesis, a framework is introduced as a novel approach for the design, prototyping and evaluation of mobile interfaces for domestic environments. Included within this framework are three components. Firstly, the Reconfigurable Multimedia Environment (RME), a physical evaluation and observation space for conducting user centred research. Secondly, Simulated Interactive Devices (SID), a video-based development and control tool for simulating interactive devices commonly found within a smart home. Thirdly, iProto, a tool that facilitates the production and rapid deployment of high fidelity prototypes for mobile touch screen devices. This framework is evaluated as a round-tripping toolchain for prototyping smart home control and found to be an efficient process for facilitating the design and evaluation of such interfaces

A tool for rapid MAC protocols prototyping and designing for wireless sensor networks

Wireless Sensor Networks (WSNs)consists of several resource constrained sensor nodes distributed over an specific geographical area. WSNs are typically energy constraint due to the fact the sensor nodes are battery powered. Medium Access Control (MAC) protocols used in WSNs are usually designed to be power aware, i.e., they are more energy efficient than MAC protocols used for other ad-hoc wireless networks such as IEEE 802.11 [2]; to increase the lifetime of the nodes. Traditional MAC protocol implementations are done for specific hardware platforms using a monolithic approach. Therefore, it is very difficult to port from one platform to another without modifying the whole implementation protocol. This reduces code reusage and increases the implementation efforts. We have designed and implemented a toolchain which allows to design and prototype MAC protocols for WSNs in a simple manner. In addition, it allows non-specific sensors users to implement and execute them in sensor nodes without worrying about technical specifications of the platforms. The toolchain has been implemented in TinyOS using a component-based design. Special care has been taken to ensure hardware independence of the protocol implementations described in this thesis has been integrated with [1] to allow runtime reconfiguration of MAC protocols. We have evaluated our toolchain against monolithic implementations in terms of memory consumption and execution time. The results show that the toolchain introduces an acceptable memory and execution time overhead, less than 5 %, compared to the monolithic approach and substantially eases the implementation efforts

Programmable logic devices in sensor networks: a survey

This paper presents a survey about the use of reconfigurable hardware technologies in sensor networks, considering proposals published in two of the leading conferences of Programmable Logic Devices: FPL and SPL. These proposals cover different applications such as wireless communications, different networks topics and sensors. Some of the papers considered in this survey are directly related with WSN, such as reconfigurable nodes or lowpower hardware platforms intended for sensor networks. Other papers are not directly related to WSN, but they present results and concepts that may be of interest in the field of the WSNs.Sociedad Argentina de Informática e Investigación Operativ

Runtime Hardware Reconfiguration in Wireless Sensor Networks for Condition Monitoring

The integration of miniaturized heterogeneous electronic components has enabled the deployment of tiny sensing platforms empowered by wireless connectivity known as wireless sensor networks. Thanks to an optimized duty-cycled activity, the energy consumption of these battery-powered devices can be reduced to a level where several years of operation is possible. However, the processing capability of currently available wireless sensor nodes does not scale well with the observation of phenomena requiring a high sampling resolution. The large amount of data generated by the sensors cannot be handled efficiently by low-power wireless communication protocols without a preliminary filtering of the information relevant for the application. For this purpose, energy-efficient, flexible, fast and accurate processing units are required to extract important features from the sensor data and relieve the operating system from computationally demanding tasks. Reconfigurable hardware is identified as a suitable technology to fulfill these requirements, balancing implementation flexibility with performance and energy-efficiency. While both static and dynamic power consumption of field programmable gate arrays has often been pointed out as prohibitive for very-low-power applications, recent programmable logic chips based on non-volatile memory appear as a potential solution overcoming this constraint. This thesis first verifies this assumption with the help of a modular sensor node built around a field programmable gate array based on Flash technology. Short and autonomous duty-cycled operation combined with hardware acceleration efficiently drop the energy consumption of the device in the considered context. However, Flash-based devices suffer from restrictions such as long configuration times and limited resources, which reduce their suitability for complex processing tasks. A template of a dynamically reconfigurable architecture built around coarse-grained reconfigurable function units is proposed in a second part of this work to overcome these issues. The module is conceived as an overlay of the sensor node FPGA increasing the implementation flexibility and introducing a standardized programming model. Mechanisms for virtual reconfiguration tailored for resource-constrained systems are introduced to minimize the overhead induced by this genericity. The definition of this template architecture leaves room for design space exploration and application- specific customization. Nevertheless, this aspect must be supported by appropriate design tools which facilitate and automate the generation of low-level design files. For this purpose, a software tool is introduced to graphically configure the architecture and operation of the hardware accelerator. A middleware service is further integrated into the wireless sensor network operating system to bridge the gap between the hardware and the design tools, enabling remote reprogramming and scheduling of the hardware functionality at runtime. At last, this hardware and software toolchain is applied to real-world wireless sensor network deployments in the domain of condition monitoring. This category of applications often require the complex analysis of signals in the considered range of sampling frequencies such as vibrations or electrical currents, making the proposed system ideally suited for the implementation. The flexibility of the approach is demonstrated by taking examples with heterogeneous algorithmic specifications. Different data processing tasks executed by the sensor node hardware accelerator are modified at runtime according to application requests