HADES-1: A rapid prototyping environment based on advanced FPGA’s

Rapid prototyping of large digital systems is becoming supported with the use of new advanced FPGA's. These FPGA's can give more Information than functional simulation and emulation tasks, due to their inner inspection features. This paper presents HADES-l, a new environment for rapid prototyping and hardware debugging. HADES-l is based on one FPGA of the VIRTEX family, exploiting the advanced features of the SelectMap port and a fast link with the host PC

Improving the design process of VLSI circuits by means of a hardware debugging system: UNSHADES-1 framework

Due to the increase in size and complexity of VLSI integrated circuits, new design tools are becoming needed. Telecommunications and Electronic Industry demand designs that integrate intensive digital signal processing blocks and complex control tasks. Rapid Prototyping techniques introduce a new stage into the design flow that overcome the drawbacks of simulation stage and shorten design times. Advanced FPGAs can host the design for its emulation and can run inserted into the final system. The benefits of their use go beyond the simple rapid prototyping approach, and are able to provide additional information and other useful tasks that will be presented in this paper

Implementation Of Modular Testing In Bios Development And Debug

This project presents a modular approach in BIOS development in purpose to tackle the problem of long development time with the existing methodologies which are hardware platform approach and virtual platform approach. The proposed approach consists of previous generation platform, a FPGA card and UEFI drivers. The FPGA is loaded with the RTL of one Intellectual Property (IP) from the current company project. The chosen IP is Low Power Subsystem (LPSS). The card is then plugged into the PCI slot of the platform. Besides, UEFI Configuration Driver and UEFI Reset Driver are built to configure and reset the LPSS registers respectively. Both of them are stored into a thumb drive and plugged into USB port of the platform. They are executed in the UEFI Shell environment. In this project, the development time of LPSS needed by the three methodologies which are hardware platform approach, virtual platform approach and modular approach are compared. The results indicate that modular approach is capable to save up to 90% of the development time in comparison with the other two approaches. At the same time, both of the UEFI drivers are functioning correctly. The processing time of both of the UEFI Configuration Driver and UEFI Reset Driver are about 1 to 2 seconds only. In conclusion, the novelty of the modular approach is that the BIOS can be developed in modular basis, without having to develop the BIOS as a whole. Therefore, it is able to cut down the BIOS development time efficientl

Hardware Simulator Design for MIMO Propagation Channel on Shipboard at 2.2 GHz

27 pagesInternational audienceA wireless communication system can be tested either in actual conditions or with a hardware simulator reproducing actual conditions. With a hardware simulator it is possible to freely simulate a desired radio channel, making it possible to test "on table" mobile radio equipments. This paper presents new architectures for the digital block of a hardware simulator ofMIMO propagation channels. This simulator can be used for LTE and WLAN IEEE 802.11ac applications, in indoor and outdoor environments. However, in this paper, specific architectures of the digital block of the simulator for shipboard environment are presented. A hardware simulator must reproduce the behavior of the radio propagation channel. Thus, ameasurements campaign has been conducted to obtain the impulse responses of the shipboard channel using a channel sounder designed and realized at IETR. After the presentation of the channel sounder, the channel impulse responses are described and implemented. Then, the new architectures of the digital block of the hardware simulator, implemented on a Xilinx Virtex-IV FPGA are presented. The accuracy, the occupation on the FPGA and the latency of the architectures are analyzed

MIMO Hardware Simulator Design for Outdoor Time-Varying Heterogeneous Channels

1-4International audienceThis paper presents a hardware simulator of Multiple- Input Multiple-Output (MIMO) propagation channels. The hardware simulator reproduces a desired radio channel and makes it possible to test "on table" different MIMO systems. A specific architecture of the digital block of the simulator is presented to characterize an outdoor scenario for Long Term Evolution (LTE) systems. An algorithm is introduced to switch between the impulse responses and to control the time variation of the delays. The new architecture is designed on a Xilinx Virtex-IV Field Programmable Gate Array (FPGA). Its accuracy, occupation on the FPGA and latency are analyzed

MATLAB as a Design and Verification Tool for the Hardware Prototyping of Wireless Communication Systems

Peer ReviewedPostprint (published version