188 research outputs found
Delta-Sigma Digitization and Optical Coherent Transmission of DOCSIS 3.1 Signals in Hybrid Fiber Coax Networks
We first demonstrate delta-sigma digitization and coherent transmission of data over cable system interface specification (DOCSIS) 3.1 signals in a hybrid fiber coax (HFC) network. Twenty 192-MHz DOCSIS 3.1 channels with modulation up to 16384QAM are digitized by a low-pass cascade resonator feedback (CRFB) delta-sigma analog-to-digital converter (ADC) and transmitted over 80 km fiber using coherent single-λ 128-Gb/s dual-polarization (DP)-QPSK and 256-Gb/s DP-16QAM optical links. Both one-bit and two-bit delta-sigma digitization are implemented and supported by the QPSK and 16QAM coherent transmission systems, respectively. To facilitate its practical application in access networks, the coherent system is built using a low-cost narrowband optical modulator and RF amplifiers. Modulation error ratio (MER) larger than 50 dB is successfully demonstrated for all 20 DOCSIS 3.1 channels, and high order modulation up to 16384QAM is delivered over fiber for the first time in HFC networks. The raw DOCSIS data capacity is 54 Gb/s with net user information ~45 Gb/s. Moreover, the bit error ratio (BER) tolerance is evaluated by measuring the MER performance as BER increases. Negligible MER degradation is observed for BER up to 1.5 × 10−6 and 1.7 × 10−4, for one-bit and two-bit digitization, respectively
Nonlinear impairments and mitigation technologies for the next generation fiber-wireless mobile fronthaul networks
The proliferation of Internet-connected mobile devices and video-intensive services are driving the growth of mobile data traffic in an explosive way. The last mile of access networks, mobile fronthaul (MFH) networks, have become the data rate bottleneck of user experience. The objective of this research are two-fold. For analog MFH, nonlinear interferences among multiple bands of mobile signals in a multi-RAT multi-service radio-over-fiber (RoF)-based MFH system are investigated for the first time. The nonlinear impairments of both single-carrier and multi-carrier signals are investigated, and it is experimentally demonstrated that inter-channel interferences play a more important role in the performance degradation of analog MFH than the nonlinear distortions of each individual signal. A digital predistortion technique was also presented to linearize the analog MFH links. On the other hand, for digital MFH, we experimentally demonstrate a novel digitization interface based on delta-sigma modulation to replace the state-of-the-art common public radio interface (CPRI). Compared with CPRI, it provides improved spectral efficiency and enhanced fronthaul capacity, and can accommodate both 4G-LTE and 5G mobile services.Ph.D
High-Bandwidth Voltage-Controlled Oscillator based architectures for Analog-to-Digital Conversion
The purpose of this thesis is the proposal and implementation of data conversion
open-loop architectures based on voltage-controlled oscillators (VCOs) built with
ring oscillators (RO-based ADCs), suitable for highly digital designs, scalable to
the newest complementary metal-oxide-semiconductor (CMOS) nodes.
The scaling of the design technologies into the nanometer range imposes the
reduction of the supply voltage towards small and power-efficient architectures,
leading to lower voltage overhead of the transistors. Additionally, phenomena
like a lower intrinsic gain, inherent noise, and parasitic effects (mismatch between
devices and PVT variations) make the design of classic structures for ADCs more
challenging. In recent years, time-encoded A/D conversion has gained relevant
popularity due to the possibility of being implemented with mostly digital structures.
Within this trend, VCOs designed with ring oscillator based topologies
have emerged as promising candidates for the conception of new digitization
techniques.
RO-based data converters show excellent scalability and sensitivity, apart from
some other desirable properties, such as inherent quantization noise shaping and
implicit anti-aliasing filtering. However, their nonlinearity and the limited time
delay achievable in a simple NOT gate drastically limits the resolution of the converter,
especially if we focus on wide-band A/D conversion. This thesis proposes
new ways to alleviate these issues.
Firstly, circuit-based techniques to compensate for the nonlinearity of the ring
oscillator are proposed and compared to equivalent state-of-the-art solutions.
The proposals are designed and simulated in a 65-nm CMOS node for open-loop
RO-based ADC architectures. One of the techniques is also validated experimentally
through a prototype. Secondly, new ways to artificially increase the effective
oscillation frequency are introduced and validated by simulations. Finally, new
approaches to shape the quantization noise and filter the output spectrum of a
RO-based ADC are proposed theoretically. In particular, a quadrature RO-based
band-pass ADC and a power-efficient Nyquist A/D converter are proposed and
validated by simulations.
All the techniques proposed in this work are especially devoted for highbandwidth
applications, such as Internet-of-Things (IoT) nodes or maximally
digital radio receivers. Nevertheless, their field of application is not restricted to
them, and could be extended to others like biomedical instrumentation or sensing.El propósito de esta tesis doctoral es la propuesta y la implementación de arquitecturas
de conversión de datos basadas en osciladores en anillos, compatibles
con diseños mayoritariamente digitales, escalables en los procesos CMOS de fabricación
más modernos donde las estructuras digitales se ven favorecidas.
La miniaturización de las tecnologías CMOS de diseño lleva consigo la reducción
de la tensión de alimentación para el desarrollo de arquitecturas pequeñas
y eficientes en potencia. Esto reduce significativamente la disponibilidad de tensión
para saturar transistores, lo que añadido a una ganancia cada vez menor
de los mismos, ruido y efectos parásitos como el “mismatch” y las variaciones
de proceso, tensión y temperatura han llevado a que sea cada vez más complejo
el diseño de estructuras analógicas eficientes. Durante los últimos años la conversión
A/D basada en codificación temporal ha ganado gran popularidad dado
que permite la implementación de estructuras mayoritariamente digitales. Como
parte de esta evolución, los osciladores controlados por tensión diseñados con topologías
de oscilador en anillo han surgido como un candidato prometedor para
la concepción de nuevas técnicas de digitalización.
Los convertidores de datos basados en osciladores en anillo son extremadamente
sensibles (variación de frecuencia con respecto a la señal de entrada) así como
escalables, además de otras propiedades muy atractivas, como el conformado
espectral de ruido de cuantificación y el filtrado “anti-aliasing”. Sin embargo, su
respuesta no lineal y el limitado tiempo de retraso alcanzable por una compuerta
NOT restringen la resolución del conversor, especialmente para conversión A/D
en aplicaciones de elevado ancho de banda. Esta tesis doctoral propone nuevas
técnicas para aliviar este tipo de problemas.
En primer lugar, se proponen técnicas basadas en circuito para compensar el
efecto de la no linealidad en los osciladores en anillo, y se comparan con soluciones
equivalentes ya publicadas. Las propuestas se diseñan y simulan en tecnología
CMOS de 65 nm para arquitecturas en lazo abierto. Una de estas técnicas
presentadas es también validada experimentalmente a través de un prototipo.
En segundo lugar, se introducen y validan por simulación varias formas de incrementar
artificialmente la frecuencia de oscilación efectiva. Para finalizar, se
proponen teóricamente dos enfoques para configurar nuevas formas de conformación
del ruido de cuantificación y filtrado del espectro de salida de los datos
digitales. En particular, son propuestos y validados por simulación un ADC pasobanda
en cuadratura de fase y un ADC de Nyquist de gran eficiencia en potencia. Todas las técnicas propuestas en este trabajo están destinadas especialmente
para aplicaciones de alto ancho de banda, tales como módulos para el Internet
de las cosas o receptores de radiofrecuencia mayoritariamente digitales. A pesar
de ello, son extrapolables también a otros campos como el de la instrumentación
biomédica o el de la medición de señales mediante sensores.Programa de Doctorado en Ingeniería Eléctrica, Electrónica y Automática por la Universidad Carlos III de MadridPresidente: Juan Pablo Alegre Pérez.- Secretario: Celia López Ongil.- Vocal: Fernando Cardes Garcí
PROCESS AWARE ANALOG-CENTRIC SINGLE LEAD ECG ACQUISITION AND CLASSIFICATION CMOS FRONTEND
The primary objective of this research work is the development of a low power single-lead ECG
analog front-end (AFE) architecture which includes acquisition, digitization, process aware efficient
gain and frequency control mechanism and a low complexity classifier for the detecting asystole,
extreme bardycardia and tachycardia. Recent research on ECG recording systems focuses on the
design of a compact single-lead wearable/portable devices with ultra-low-power consumption and
in-built hardware for diagnosis and prognosis. Since, the amplitude of the ECG signal varies from
hundreds of µV to a few mV, and has a bandwidth of DC to 250 Hz, conventional front-ends use
an instrument amplifier followed by a programmable gain amplifier (PGA) to amplify the input
ECG signal appropriately. This work presents an mixed signal ECG fronted with an ultra-low
power two-stage capacitive-coupled signal conditioning circuit (or an AFE), providing programmable
amplification along with tunable 2nd order high pass and lowpass filter characteristics. In the
contemporary state-of-the-art ECG recording systems, the gain of the amplifier is controlled by
external digital control pins which are in turn dynamically controlled through a DSP. Therefore, an
efficient automatic gain control mechanism with minimal area overhead and consuming power in the
order of nano watts only. The AGC turns the subsequent ADC on only after output of the PGA (or
input of the ADC) reaches a level for which the ADC achieves maximum signal-to-noise-ratio (SNR),
hence saving considerable startup power and avoiding the use of DSP. Further, in any practical filter
design, the low pass cut-off frequency is prone to deviate from its nominal value across process
and temperature variations. Therefore, post-fabrication calibration is essential, before the signal
is fed to an ADC, to minimize this deviation, prevent signal degradation due to aliasing of higher
frequencies into the bandwidth
for classification of ECG signals, to switch to low resolution processing, hence saving power and
enhances battery lifetime. Another short-coming noticed in the literature published so far is that
the classification algorithm is implemented in digital domain, which turns out to be a power hungry
approach. Moreover, Although analog domain implementations of QRS complexes detection schemes
have been reported, they employ an external micro-controller to determine the threshold voltage. In
this regard, finally a power-efficient low complexity CMOS fully analog classifier architecture and a
heart rate estimator is added to the above scheme. It reduces the overall system power consumption
by reducing the computational burden on the DSP. The complete proposed scheme consists of (i)
an ultra-low power QRS complex detection circuit using an autonomous dynamic threshold voltage,
hence discarding the need of any external microcontroller/DSP and calibration (ii) a power efficient
analog classifier for the detection of three critical alarm types viz. asystole, extreme bradycardia
and tachycardia. Additionally, a heart rate estimator that provides the number of QRS complexes
within a period of one minute for cardiac rhythm (CR) and heart rate variability (HRV) analysis.
The complete proposed architecture is implemented in UMC 0.18 µm CMOS technology with 1.8 V
supply. The functionality of each of the individual blocks are successfully validated using postextraction
process corner simulations and through real ECG test signals taken from the PhysioNet
database. The capacitive feedback amplifier, Σ∆ ADC, AGC and the AFT are fabricated, and the
measurement results are discussed here. The analog classification scheme is successfully validated
using embed NXP LPC1768 board, discrete peak detector prototype and FPGA software interfac
Design and analysis of multi-element antenna systems and agile radiofrequency frontends for automotive applications
Vehicular connectivity serves as one of the major enabling technologies for
current applications like driver assistance, safety and infotainment as well as
upcoming features like highly automated vehicles - all of which having certain
quality of service requirements, e. g. datarate or reliability. This work focuses on
vehicular integration of multiple-input-multiple-output (MIMO) capable multielement
antenna systems and frequency-agile radio frequency (RF) front ends
to cover current and upcoming connectivity needs. It is divided in four major
parts. For each part, mostly physical layer effects are analyzed (any performance
lost on physical layer, cannot be compensated in higher layers), sensitivities are
identified and novel concepts are introduced based on the status-quo findings.Fahrzeugvernetzung dient als eine der wesentlichsten Befähigungstechnologien
für moderne Fahrerassistenzsysteme und zukünftig auch hochautomatisiertes
Fahren. Sowohl die heutigen als auch zukünftige Anwendungen haben besondere
Dienstgüteanforderungen, z.B. in Bezug auf die Datenrate oder Verlässlichkeit.
Im Rahmen dieser Arbeit wird die Integration von Mehrantennensystemen für
MIMO-Funkanwendungen (MIMO: engl. Multiple Input Multiple Output) sowie
von frequenzagilen Hochfrequenzfrontends im Fahrzeugumfeld untersucht, um
so eine technische Grundlage für zukünftige Anforderungen an die automobile
Vernetzung anbieten zu können. Die dabei gewonnenen Erkenntnisse lassen sich
in vier Teile gliedern. Grundsätzlich konzentrieren sich die Untersuchungen vorrangig
auf die physikalische Ebene. Auf Basis des aktuellen Status Quo werden
Sensitivitäten herausgearbeitet, neue Konzepte hergeleitet und entwickelt
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