Optimizing the integration and energy efficiency of through silicon via-based 3D interconnects

The aggressive scaling of CMOS process technology has been driving the rapid growth of the semiconductor industry for more than three decades. In recent years, the performance gains enabled by CMOS scaling have been increasingly challenged by highlyparasitic on-chip interconnects as wire parasitics do not scale at the same pace. Emerging 3D integration technologies based on vertical through-silicon vias (TSVs) promise a solution to the interconnect performance bottleneck, along with reduced fabrication cost and heterogeneous integration. As TSVs are a relatively recent interconnect technology, innovative test structures are required to evaluate and optimise the process, as well as extract parameters for the generation of design rules and models. From the circuit designer’s perspective, critical TSV characteristics are its parasitic capacitance, and thermomechanical stress distribution. This work proposes new test structures for extracting these characteristics. The structures were fabricated on a 65nm 3D process and used for the evaluation of that technology. Furthermore, as TSVs are implemented in large, densely interconnected 3D-system-on-chips (SoCs), the TSV parasitic capacitance may become an important source of energy dissipation. Typical low-power techniques based on voltage scaling can be used, though this represents a technical challenge in modern technology nodes. In this work, a novel TSV interconnection scheme is proposed based on reversible computing, which shows frequencydependent energy dissipation. The scheme is analysed using theoretical modelling, while a demonstrator IC was designed based on the developed theory and fabricated on a 130nm 3D process.EThOS - Electronic Theses Online ServiceEngineering and Physical Science Research Council (EPSRC)GBUnited Kingdo

Embedded toggle generator to control the switching activity during test of digital 2D-SoCs and 3D-SICs

In digital logic circuits, unconstrained scan tests are known to evoke much higher switching activity than functional modes. To create test conditions which are as similar as possible to functional modes, today’s ATPG tools have knobs to constrain the switching activity of the generated test to a user-defined\u3cbr/\u3efunctional (= lower) level. Two-dimensional system chips (SoCs) and three-dimensional stacked ICs (SICs) are typically tested in a modular fashion, i.e., per embedded core or stacked die. At any moment during the test, one or more modules are being tested(‘module-under-test’, MUT); we refer to the modules currently not being tested as ‘neighbors’. The switching activity of the MUT(s) can be controlled by ATPG constraints, but the switching activity of the neighboring modules is typically not controlled. In this work, we present two key elements for an approach to con13431trol the switching activity of both MUT(s) and neighboring modules. The first is a toggle analysis tool, that determines the switching activity of a module in either functional or test mode on the basis of a Value Change Dump (.vcd) file generated during gate-level Verilog netlist simulation. The second element is a programmable on-chip toggle generator, for which we present both its hardware scheme, as well as an algorithm to program it to achieve any target switching activity. For each module, the toggle analysis\u3cbr/\u3etool can be used to determine the switching activity in functional\u3cbr/\u3emode, which then forms the target for the ATPG tool when the\u3cbr/\u3emodule is a MUT, or for its embedded toggle generator while\u3cbr/\u3ethe module is in its role as neighbor.\u3cbr/\u3e\u3cbr/\u3

Embedded toggle generator to control the switching activity during test of digital 2D-SoCs and 3D-SICs

In digital logic circuits, unconstrained scan tests are known to evoke much higher switching activity than functional modes. To create test conditions which are as similar as possible to functional modes, today’s ATPG tools have knobs to constrain the switching activity of the generated test to a user-defined functional (= lower) level. Two-dimensional system chips (SoCs) and three-dimensional stacked ICs (SICs) are typically tested in a modular fashion, i.e., per embedded core or stacked die. At any moment during the test, one or more modules are being tested(‘module-under-test’, MUT); we refer to the modules currently not being tested as ‘neighbors’. The switching activity of the MUT(s) can be controlled by ATPG constraints, but the switching activity of the neighboring modules is typically not controlled. In this work, we present two key elements for an approach to con13431trol the switching activity of both MUT(s) and neighboring modules. The first is a toggle analysis tool, that determines the switching activity of a module in either functional or test mode on the basis of a Value Change Dump (.vcd) file generated during gate-level Verilog netlist simulation. The second element is a programmable on-chip toggle generator, for which we present both its hardware scheme, as well as an algorithm to program it to achieve any target switching activity. For each module, the toggle analysis tool can be used to determine the switching activity in functional mode, which then forms the target for the ATPG tool when the module is a MUT, or for its embedded toggle generator while the module is in its role as neighbor