1,515 research outputs found
SInCom 2015
2nd Baden-WĂĽrttemberg Center of Applied Research Symposium on Information and Communication Systems, SInCom 2015, 13. November 2015 in Konstan
Development of an oceanographic application in HPC
High Performance Computing (HPC) is used for running advanced application programs
efficiently, reliably, and quickly.
In earlier decades, performance analysis of HPC applications was evaluated based on
speed, scalability of threads, memory hierarchy. Now, it is essential to consider the
energy or the power consumed by the system while executing an application.
In fact, the High Power Consumption (HPC) is one of biggest problems for the High
Performance Computing (HPC) community and one of the major obstacles for exascale
systems design.
The new generations of HPC systems intend to achieve exaflop performances and will
demand even more energy to processing and cooling. Nowadays, the growth of HPC
systems is limited by energy issues
Recently, many research centers have focused the attention on doing an automatic tuning
of HPC applications which require a wide study of HPC applications in terms of power
efficiency.
In this context, this paper aims to propose the study of an oceanographic application,
named OceanVar, that implements Domain Decomposition based 4D Variational model
(DD-4DVar), one of the most commonly used HPC applications, going to evaluate not
only the classic aspects of performance but also aspects related to power efficiency in
different case of studies.
These work were realized at Bsc (Barcelona Supercomputing Center), Spain within the
Mont-Blanc project, performing the test first on HCA server with Intel technology and then on a mini-cluster Thunder with ARM technology.
In this work of thesis it was initially explained the concept of assimilation date, the
context in which it is developed, and a brief description of the mathematical model
4DVAR.
After this problem’s close examination, it was performed a porting from Matlab
description of the problem of data-assimilation to its sequential version in C language.
Secondly, after identifying the most onerous computational kernels in order of time, it
has been developed a parallel version of the application with a parallel multiprocessor
programming style, using the MPI (Message Passing Interface) protocol.
The experiments results, in terms of performance, have shown that, in the case of
running on HCA server, an Intel architecture, values of efficiency of the two most
onerous functions obtained, growing the number of process, are approximately equal to
80%.
In the case of running on ARM architecture, specifically on Thunder mini-cluster,
instead, the trend obtained is labeled as "SuperLinear Speedup" and, in our case, it can
be explained by a more efficient use of resources (cache memory access) compared with
the sequential case.
In the second part of this paper was presented an analysis of the some issues of this
application that has impact in the energy efficiency.
After a brief discussion about the energy consumption characteristics of the Thunder
chip in technological landscape, through the use of a power consumption detector, the
Yokogawa Power Meter, values of energy consumption of mini-cluster Thunder were
evaluated in order to determine an overview on the power-to-solution of this application
to use as the basic standard for successive analysis with other parallel styles.
Finally, a comprehensive performance evaluation, targeted to estimate the goodness of
MPI parallelization, is conducted using a suitable performance tool named Paraver,
developed by BSC.
Paraver is such a performance analysis and visualisation tool which can be used to
analyse MPI, threaded or mixed mode programmes and represents the key to perform a parallel profiling and to optimise the code for High Performance Computing.
A set of graphical representation of these statistics make it easy for a developer to
identify performance problems. Some of the problems that can be easily identified are
load imbalanced decompositions, excessive communication overheads and poor average
floating operations per second achieved.
Paraver can also report statistics based on hardware counters, which are provided by the
underlying hardware.
This project aimed to use Paraver configuration files to allow certain metrics to be
analysed for this application.
To explain in some way the performance trend obtained in the case of analysis on the
mini-cluster Thunder, the tracks were extracted from various case of studies and the
results achieved is what expected, that is a drastic drop of cache misses by the case ppn
(process per node) = 1 to case ppn = 16.
This in some way explains a more efficient use of cluster resources with an increase of
the number of processes
An Embedded Biometric Sensor for Ubiquitous Authentication
Communication networks and distributed technologies
move people towards the era of ubiquitous computing. An
ubiquitous environment needs many authentication sensors for
users recognition, in order to provide a secure infrastructure for
both user access to resources and services and information
management. Today the security requirements must ensure
secure and trusted user information to protect sensitive data
resource access and they could be used for user traceability inside
the platform. Conventional authentication systems, based on
username and password, are in crisis since they are not able to
guarantee a suitable security level for several applications.
Biometric authentication systems represent a valid alternative to
the conventional authentication systems providing a flexible einfrastructure
towards an integrated solution supporting the
requirement for improved inter-organizational functionality. In
this work the study and the implementation of a fingerprintsbased
embedded biometric system is proposed. Typical strategies
implemented in Identity Management Systems could be useful to
protect biometric information. The proposed sensor can be seen
as a self-contained sensor: it performs the all elaboration steps on
board, a necessary requisite to strengthen security, so that
sensible data are securely managed and stored inside the sensor,
without any data leaking out. The sensor has been prototyped via
an FPGA-based platform achieving fast execution time and a
good final throughput. Resources used, elaboration times of the
sensor are reported. Finally, recognition rates of the proposed
embedded biometric sensor have been evaluated considering
three different databases: the FVC2002 reference database, the
CSAI/Biometrika proprietary database, and the CSAI/Secugen
proprietary database. The best achieved FAR and FRR indexes
are respectively 1.07% and 8.33%, with an elaboration time of
183.32 ms and a working frequency of 22.5 MHz
A Sorting Hat For Clusters. Dynamic Provisioning of Compute Nodes for Colocated Large Scale Computational Research Infrastructures
Current large scale computational research infrastructures are composed of multitudes
of compute nodes fitted with similar or identical hardware. For practical
purposes, the deployment of the software operating environment to each compute
node is done in an automated fashion. If a data centre hosts more than one of
these systems – for example cloud and HPC clusters – it is beneficial to use the
same provisioning method for all of them. The uniform provisioning approach
unifies administration of the various systems and allows flexible dedication and
reconfiguration of computational resources. In particular, we will highlight the
requirements on the underlying network infrastructure for unified remote boot
but segregated service operations. Building upon this, we will present the Boot
Selection Service, allowing for the addition, removal or rededication of a node to
a given research infrastructure with a simple reconfiguration
Predictable migration and communication in the Quest-V multikernal
Quest-V is a system we have been developing from the ground up, with objectives focusing on safety, predictability and efficiency. It is designed to work on emerging multicore processors with hardware virtualization support. Quest-V is implemented as a ``distributed system on a chip'' and comprises multiple sandbox kernels. Sandbox kernels are isolated from one another in separate regions of physical memory, having access to a subset of processing cores and I/O devices. This partitioning prevents system failures in one sandbox affecting the operation of other sandboxes. Shared memory channels managed by system monitors enable inter-sandbox communication.
The distributed nature of Quest-V means each sandbox has a separate physical clock, with all event timings being managed by per-core local timers. Each sandbox is responsible for its own scheduling and I/O management, without requiring intervention of a hypervisor. In this paper, we formulate bounds on inter-sandbox communication in the absence of a global scheduler or global system clock. We also describe how address space migration between sandboxes can be guaranteed without violating service constraints. Experimental results on a working system show the conditions under which Quest-V performs real-time communication and migration.National Science Foundation (1117025
Technologies and Applications for Big Data Value
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