Low-Power and Programmable Analog Circuitry for Wireless Sensors

Embedding networks of secure, wirelessly-connected sensors and actuators will help us to conscientiously manage our local and extended environments. One major challenge for this vision is to create networks of wireless sensor devices that provide maximal knowledge of their environment while using only the energy that is available within that environment. In this work, it is argued that the energy constraints in wireless sensor design are best addressed by incorporating analog signal processors. The low power-consumption of an analog signal processor allows persistent monitoring of multiple sensors while the device\u27s analog-to-digital converter, microcontroller, and transceiver are all in sleep mode. This dissertation describes the development of analog signal processing integrated circuits for wireless sensor networks. Specific technology problems that are addressed include reconfigurable processing architectures for low-power sensing applications, as well as the development of reprogrammable biasing for analog circuits

Low-Power and Programmable Analog Circuitry for Wireless Sensors

Embedding networks of secure, wirelessly-connected sensors and actuators will help us to conscientiously manage our local and extended environments. One major challenge for this vision is to create networks of wireless sensor devices that provide maximal knowledge of their environment while using only the energy that is available within that environment. In this work, it is argued that the energy constraints in wireless sensor design are best addressed by incorporating analog signal processors. The low power-consumption of an analog signal processor allows persistent monitoring of multiple sensors while the device\u27s analog-to-digital converter, microcontroller, and transceiver are all in sleep mode. This dissertation describes the development of analog signal processing integrated circuits for wireless sensor networks. Specific technology problems that are addressed include reconfigurable processing architectures for low-power sensing applications, as well as the development of reprogrammable biasing for analog circuits

Measurements, Models, Systems and Design

531 s.

Reconfigurable Gate Driver Toward High-Power Efficiency and High-Power Density Converters

Les systèmes de gestion de l'énergie exigent des convertisseurs de puissance pour fournir une conversion de puissance adaptée à diverses utilisations. Il existe différents types de convertisseurs de puissance, tel que les amplificateurs de puissance de classe D, les demi-ponts, les ponts complets, les amplificateurs de puissance de classe E, les convertisseurs buck et dernièrement les convertisseurs boost. Prenons par exemple les dispositifs implantables, lorsque l'énergie est prélevée de la source principale, des convertisseurs de puissance buck ou boost sont nécessaires pour traiter l'énergie de l'entrée et fournir une énergie propre et adaptée aux différentes parties du système. D'autre part, dans les stations de charge des voitures électriques, les nouveaux téléphones portables, les stimulateurs neuronaux, etc., l'énergie sans fil a été utilisée pour assurer une alimentation à distance, et des amplificateurs de puissance de classe E sont développés pour accomplir cette tâche. Les amplificateurs de puissance de classe D sont un excellent choix pour les casques d'écoute ou les haut-parleurs en raison de leur grande efficacité. Dans le cas des interfaces de capteurs, les demi-ponts et les ponts complets sont les interfaces appropriées entre les systèmes à faible et à forte puissance. Dans les applications automobiles, l'interface du capteur reçoit le signal du côté puissance réduite et le transmet à un réseau du côté puissance élevée. En outre, l'interface du capteur doit recevoir un signal du côté haute puissance et le convertir vers la côté basse puissance. Tous les systèmes mentionnés ci-dessus nécessitent l'inclusion d'un pilote de porte spécifique dans les circuits, selon les applications. Les commandes de porte comprennent généralement un décalage du niveau de commande niveau supérieur, le levier de changement de niveau inférieur, une chaîne de tampon, un circuit de verrouillage sous tension, un circuit de temps mort, des portes logiques, un inverseur de Schmitt et un mécanisme de démarrage. Ces circuits sont nécessaires pour assurer le bon fonctionnement des systèmes de conversion de puissance. Un circuit d'attaque de porte reconfigurable prendrait en charge une vaste gamme de convertisseurs de puissance ayant une tension d'entrée V[indice IN] et un courant de sortie I[indice Load] variables. L'objectif de ce projet est d'étudier intensivement les causes de différentes pertes dans les convertisseurs de puissance et de proposer ensuite de nouveaux circuits et méthodologies dans les différents circuits des conducteurs de porte pour atteindre une conversion de puissance avec une haute efficacité et densité de puissance. Nous proposons dans cette thèse de nouveaux circuits de gestion des temps mort, un Shapeshifter de niveau plus élevé et un Shapeshifter de niveau inférieur avec de nouvelles topologies qui ont été pleinement caractérisées expérimentalement. De plus, l'équation mathématique du temps mort optimal pour les faces haute et basse d'un convertisseur buck est dérivée et expérimentalement prouvée. Les circuits intégrés personnalisés et les méthodologies proposées sont validés avec différents convertisseurs de puissance, tels que les convertisseurs semi-pont et en boucle ouverte, en utilisant des composants standard pour démontrer leur supériorité sur les solutions traditionnelles. Les principales contributions de cette recherche ont été présentées à sept conférences prestigieuses, trois articles évalués par des pairs, qui ont été publiés ou présentés, et une divulgation d'invention. Une contribution importante de ce travail recherche est la proposition d'un nouveau générateur actif CMOS intégré dédié de signaux sans chevauchement. Ce générateur a été fabriqué à l'aide de la technologie AMS de 0.35µm et consomme 16.8mW à partir d'une tension d'alimentation de 3.3V pour commander de manière appropriée les côtés bas et haut d'un demi-pont afin d'éliminer la propagation. La puce fabriquée est validée de façon expérimentale avec un demi-pont, qui a été mis en œuvre avec des composants disponibles sur le marché et qui contrôle une charge R-L. Les résultats des mesures montrent une réduction de 40% de la perte totale d'un demi-pont de 45V d'entrée à 1MHz par rapport au fonctionnement du demi-pont sans notre circuit intégré dédié. Le circuit principal du circuit d'attaque de grille côté haut est le décaleur de niveau, qui fournit un signal de grande amplitude pour le commutateur de puissance côté haut. Une nouvelle structure de décalage de niveau avec un délai de propagation minimal doit être présentée. Nous proposons une nouvelle topologie de décalage de niveau pour le côté haut des drivers de porte afin de produire des convertisseurs de puissance efficaces. Le SL présente des délais de propagation mesurés de 7.6ns. Les résultats mesurés montrent le fonctionnement du circuit présenté sur la plage de fréquence de 1MHz à 130MHz. Le circuit fabriqué consomme 31.5pW de puissance statique et 3.4pJ d'énergie par transition à 1kHz, V[indice DDL] = 0.8V , V[indice DDH] = 3.0V, et une charge capacitive C[indice L] = 0.1pF. La consommation énergétique totale mesurée par rapport à la charge capacitive de 0.1 à 100nF est indiquée. Un autre nouveau décalage vers le bas est proposé pour être utilisé sur le côté bas des pilotes de portes. Ce circuit est également nécessaire dans la partie Rₓ du réseau de bus de données pour recevoir le signal haute tension du réseau et délivrer un signal de faible amplitude à la partie basse tension. L'une des principales contributions de ces travaux est la proposition d'un modèle de référence pour l'abaissement de niveau à puissance unique reconfigurable. Le circuit proposé pilote avec succès une gamme de charges capacitives allant de 10fF à 350pF. Le circuit présenté consomme des puissances statiques et dynamiques de 62.37pW et 108.9µW, respectivement, à partir d'une alimentation de 3.3V lorsqu'il fonctionne à 1MHz et pilote une charge capacitive de 10pF. Les résultats de la simulation post-layout montrent que les délais de propagation de chute et de montée dans les trois configurations sont respectivement de l'ordre de 0.54 à 26.5ns et de 11.2 à 117.2ns. La puce occupe une surface de 80µm × 100µm. En effet, les temps morts des côtés hauts et bas varient en raison de la différence de fonctionnement des commutateurs de puissance côté haut et côté bas, qui sont respectivement en commutation dure et douce. Par conséquent, un générateur de temps mort reconfigurable asymétrique doit être ajouté aux pilotes de portes traditionnelles pour obtenir une conversion efficace. Notamment, le temps mort asymétrique optimal pour les côtés hauts et bas des convertisseurs de puissance à base de Gan doit être fourni par un circuit de commande de grille reconfigurable pour obtenir une conception efficace. Le temps mort optimal pour les convertisseurs de puissance dépend de la topologie. Une autre contribution importante de ce travail est la dérivation d'une équation précise du temps mort optimal pour un convertisseur buck. Le générateur de temps mort asymétrique reconfigurable fabriqué sur mesure est connecté à un convertisseur buck pour valider le fonctionnement du circuit proposé et l'équation dérivée. De plus le rendement d'un convertisseur buck typique avec T[indice DLH] minimum et T[indice DHL] optimal (basé sur l'équation dérivée) à I[indice Load] = 25mA est amélioré de 12% par rapport à un convertisseur avec un temps mort fixe de T[indice DLH] = T[indice DHL] = 12ns.Power management systems require power converters to provide appropriate power conversion for various purposes. Class D power amplifiers, half and full bridges, class E power amplifiers, buck converters, and boost converters are different types of power converters. Power efficiency and density are two prominent specifications for designing a power converter. For example, in implantable devices, when power is harvested from the main source, buck or boost power converters are required to receive the power from the input and deliver clean power to different parts of the system. In charge stations of electric cars, new cell phones, neural stimulators, and so on, power is transmitted wirelessly, and Class E power amplifiers are developed to accomplish this task. In headphone or speaker driver applications, Class D power amplifiers are an excellent choice due to their great efficiency. In sensor interfaces, half and full bridges are the appropriate interfaces between the low- and high-power sides of systems. In automotive applications, the sensor interface receives the signal from the low-power side and transmits it to a network on the high-power side. In addition, the sensor interface must receive a signal from the high-power side and convert it down to the low-power side. All the above-summarized systems require a particular gate driver to be included in the circuits depending on the applications. The gate drivers generally consist of the level-up shifter, the level-down shifter, a buffer chain, an under-voltage lock-out circuit, a deadtime circuit, logic gates, the Schmitt trigger, and a bootstrap mechanism. These circuits are necessary to achieve the proper functionality of the power converter systems. A reconfigurable gate driver would support a wide range of power converters with variable input voltage V[subscript IN] and output current I[subscript Load]. The goal of this project is to intensively investigate the causes of different losses in power converters and then propose novel circuits and methodologies in the different circuits of gate drivers to achieve power conversion with high-power efficiency and density. We propose novel deadtime circuits, level-up shifter, and level-down shifter with new topologies that were fully characterized experimentally. Furthermore, the mathematical equation for optimum deadtimes for the high and low sides of a buck converter is derived and proven experimentally. The proposed custom integrated circuits and methodologies are validated with different power converters, such as half bridge and open loop buck converters, using off-the-shelf components to demonstrate their superiority over traditional solutions. The main contributions of this research have been presented in seven high prestigious conferences, three peer-reviewed articles, which have been published or submitted, and one invention disclosure. An important contribution of this research work is the proposal of a novel custom integrated CMOS active non-overlapping signal generator, which was fabricated using the 0.35−µm AMS technology and consumes 16.8mW from a 3.3−V supply voltage to appropriately drive the low and high sides of the half bridge to remove the shoot-through. The fabricated chip is validated experimentally with a half bridge, which was implemented with off-the-shelf components and driving a R-L load. Measurement results show a 40% reduction in the total loss of a 45 − V input 1 − MHz half bridge compared with the half bridge operation without our custom integrated circuit. The main circuit of high-side gate driver is the level-up shifter, which provides a signal with a large amplitude for the high-side power switch. A new level shifter structure with minimal propagation delay must be presented. We propose a novel level shifter topology for the high side of gate drivers to produce efficient power converters. The LS shows measured propagation delays of 7.6ns. The measured results demonstrate the operation of the presented circuit over the frequency range of 1MHz to 130MHz. The fabricated circuit consumes 31.5pW of static power and 3.4pJ of energy per transition at 1kHz, V[subscript DDL] = 0.8V , V[subscript DDH] = 3.0V , and capacitive load C[subscript L] = 0.1pF. The measured total power consumption versus the capacitive load from 0.1pF to 100nF is reported. Another new level-down shifter is proposed to be used on the low side of gate drivers. Another new level-down shifter is proposed to be used on the low side of gate drivers. This circuit is also required in the Rₓ part of the data bus network to receive the high-voltage signal from the network and deliver a signal with a low amplitude to the low-voltage part. An essential contribution of this work is the proposal of a single supply reconfigurable level-down shifter. The proposed circuit successfully drives a range of capacitive load from 10fF to 350pF. The presented circuit consumes static and dynamic powers of 62.37pW and 108.9µW, respectively, from a 3.3 − V supply when working at 1MHz and drives a 10pF capacitive load. The post-layout simulation results show that the fall and rise propagation delays in the three configurations are in the range of 0.54 − 26.5ns and 11.2 − 117.2ns, respectively. Its core occupies an area of 80µm × 100µm. Indeed, the deadtimes for the high and low sides vary due to the difference in the operation of the high- and low-side power switches, which are under hard and soft switching, respectively. Therefore, an asymmetric reconfigurable deadtime generator must be added to the traditional gate drivers to achieve efficient conversion. Notably, the optimal asymmetric deadtime for the high and low sides of GaN-based power converters must be provided by a reconfigurable gate driver to achieve efficient design. The optimum deadtime for power converters depends on the topology. Another important contribution of this work is the derivation of an accurate equation of optimum deadtime for a buck converter. The custom fabricated reconfigurable asymmetric deadtime generator is connected to a buck converter to validate the operation of the proposed circuit and the derived equation. The efficiency of a typical buck converter with minimum T[subscript DLH] and optimal T[subscript DHL] (based on the derived equation) at I[subscript Load] = 25mA is improved by 12% compared to a converter with a fixed deadtime of T[subscript DLH] = T[subscript DHL] = 12ns

Energy management techniques for ultra-small bio-medical implants

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 167-174).Trends in the medical industry have created a growing demand for implantable medical devices. In particular, the need to provide medical professionals a means to continuously monitor bio-markers over long time scales with increased precision is paramount to efficient healthcare. To make medical implants more attractive, there is a need to reduce their size and power consumption. Small medical implants would allow for less invasive procedures and greater comfort for patients. The two primary limitations to the size of small medical implants are the batteries that provide energy to circuit and sensor components, and the antennas that enable wireless communication to terminals outside of the body. In this work we present energy management and low-power techniques to help solve the engineering challenges posed by using ultracapacitors for energy storage. A major problem with using any capacitor as an energy source is the fact that its voltage drops rapidly with decreasing charge. This leaves the circuit to cope with a large supply variation and can lead to energy being left on the capacitor when its voltage gets too low to supply a sufficient supply voltage for operation. Rather than use a single ultracapacitor, we demonstrate higher energy utilization by splitting a single capacitor into an array of capacitors that are progressively reconfigured as energy is drawn out. An energy management IC fabricated in 180-nm CMOS implements a stacking procedure that allows for more than 98% of the initial energy stored in the ultracapacitors to be removed before the output voltage drops unsuitably low for circuit operation. The second part of this work develops techniques for wide-input-range energy management. The first chip implementing stacking suffered an efficiency penalty by using a switchedcapacitor voltage regulator with only a single conversion ratio. In a second implementation, we introduce a better solution that preserves efficiency performance by using a multiple conversion ratio switched-capacitor voltage regulator. At any given input voltage from an ultracapcitor array, the switched-capacitor voltage regulator is configured to maximize efficiency. Fabricated in a 180-nm CMOS process, the chip achieves a peak efficiency of 90% and the efficiency does not fall below 70% for input voltages between 1.25 and 3 V.by William R. Sanchez.Ph.D

Advanced Statistical Modeling, Forecasting, and Fault Detection in Renewable Energy Systems

Fault detection, control, and forecasting have a vital role in renewable energy systems (Photovoltaics (PV) and wind turbines (WTs)) to improve their productivity, ef?ciency, and safety, and to avoid expensive maintenance. For instance, the main crucial and challenging issue in solar and wind energy production is the volatility of intermittent power generation due mainly to weather conditions. This fact usually limits the integration of PV systems and WTs into the power grid. Hence, accurately forecasting power generation in PV and WTs is of great importance for daily/hourly efficient management of power grid production, delivery, and storage, as well as for decision-making on the energy market. Also, accurate and prompt fault detection and diagnosis strategies are required to improve efficiencies of renewable energy systems, avoid the high cost of maintenance, and reduce risks of fire hazards, which could affect both personnel and installed equipment. This book intends to provide the reader with advanced statistical modeling, forecasting, and fault detection techniques in renewable energy systems

Energy-Efficient Receiver Design for High-Speed Interconnects

High-speed interconnects are of vital importance to the operation of high-performance computing and communication systems, determining the ultimate bandwidth or data rates at which the information can be exchanged. Optical interconnects and the employment of high-order modulation formats are considered as the solutions to fulfilling the envisioned speed and power efficiency of future interconnects. One common key factor in bringing the success is the availability of energy-efficient receivers with superior sensitivity. To enhance the receiver sensitivity, improvement in the signal-to-noise ratio (SNR) of the front-end circuits, or equalization that mitigates the detrimental inter-symbol interference (ISI) is required. In this dissertation, architectural and circuit-level energy-efficient techniques serving these goals are presented. First, an avalanche photodetector (APD)-based optical receiver is described, which utilizes non-return-to-zero (NRZ) modulation and is applicable to burst-mode operation. For the purposes of improving the overall optical link energy efficiency as well as the link bandwidth, this optical receiver is designed to achieve high sensitivity and high reconfiguration speed. The high sensitivity is enabled by optimizing the SNR at the front-end through adjusting the APD responsivity via its reverse bias voltage, along with the incorporation of 2-tap feedforward equalization (FFE) and 2-tap decision feedback equalization (DFE) implemented in current-integrating fashion. The high reconfiguration speed is empowered by the proposed integrating dc and amplitude comparators, which eliminate the RC settling time constraints. The receiver circuits, excluding the APD die, are fabricated in 28-nm CMOS technology. The optical receiver achieves bit-error-rate (BER) better than 1E−12 at −16-dBm optical modulation amplitude (OMA), 2.24-ns reconfiguration time with 5-dB dynamic range, and 1.37-pJ/b energy efficiency at 25 Gb/s. Second, a 4-level pulse amplitude modulation (PAM4) wireline receiver is described, which incorporates continuous time linear equalizers (CTLEs) and a 2-tap direct DFE dedicated to the compensation for the first and second post-cursor ISI. The direct DFE in a PAM4 receiver (PAM4-DFE) is made possible by the proposed CMOS track-and-regenerate slicer. This proposed slicer offers rail-to-rail digital feedback signals with significantly improved clock-to-Q delay performance. The reduced slicer delay relaxes the settling time constraint of the summer circuits and allows the stringent DFE timing constraint to be satisfied. With the availability of a direct DFE employing the proposed slicer, inductor-based bandwidth enhancement and loop-unrolling techniques, which can be power/area intensive, are not required. Fabricated in 28-nm CMOS technology, the PAM4 receiver achieves BER better than 1E−12 and 1.1-pJ/b energy efficiency at 60 Gb/s, measured over a channel with 8.2-dB loss at Nyquist frequency. Third, digital neural-network-enhanced FFEs (NN-FFEs) for PAM4 analog-to-digital converter (ADC)-based optical interconnects are described. The proposed NN-FFEs employ a custom learnable piecewise linear (PWL) activation function to tackle the nonlinearities with short memory lengths. In contrast to the conventional Volterra equalizers where multipliers are utilized to generate the nonlinear terms, the proposed NN-FFEs leverage the custom PWL activation function for nonlinear operations and reduce the required number of multipliers, thereby improving the area and power efficiencies. Applications in the optical interconnects based on micro-ring modulators (MRMs) are demonstrated with simulation results of 50-Gb/s and 100-Gb/s links adopting PAM4 signaling. The proposed NN-FFEs and the conventional Volterra equalizers are synthesized with the standard-cell libraries in a commercial 28-nm CMOS technology, and their power consumptions and performance are compared. Better than 37% lower power overhead can be achieved by employing the proposed NN-FFEs, in comparison with the Volterra equalizer that leads to similar improvement in the symbol-error-rate (SER) performance.</p

Design and Control of Power Converters for High Power-Quality Interface with Utility and Aviation Grids

Power electronics as a subject integrating power devices, electric and electronic circuits, control, and thermal and mechanic design, requires not only knowledge and engineering insight for each subarea, but also understanding of interface issues when incorporating these different areas into high performance converter design.Addressing these fundamental questions, the dissertation studies design and control issues in three types of power converters applied in low-frequency high-power transmission, medium-frequency converter emulated grid, and high-frequency high-density aviation grid, respectively, with the focus on discovering, understanding, and mitigating interface issues to improve power quality and converter performance, and to reduce the noise emission.For hybrid ac/dc power transmission,• Analyze the interface transformer saturation issue between ac and dc power flow under line unbalances.• Proposed both passive transformer design and active hybrid-line-impedance-conditioner to suppress this issue.For transmission line emulator,• Propose general transmission line emulation schemes with extension capability.• Analyze and actively suppress the effects of sensing/sampling bias and PWM ripple on emulation considering interfaced grid impedance.• Analyze the stability issue caused by interaction of the emulator and its interfaced impedance. A criterion that determines the stability and impedance boundary of the emulator is proposed.For aircraft battery charger,• Investigate architectures for dual-input and dual-output battery charger, and a three-level integrated topology using GaN devices is proposed to achieve high density.• Identify and analyze the mechanisms and impacts of high switching frequency, di/dt, dv/dt on sensing and power quality control; mitigate solutions are proposed.• Model and compensate the distortion due to charging transition of device junction capacitances in three-level converters.• Find the previously overlooked device junction capacitance of the nonactive devices in three-level converters, and analyze the impacts on switching loss, device stress, and current distortion. A loss calculation method is proposed using the data from the conventional double pulse tester.• Establish fundamental knowledge on performance degradation of EMI filters. The impacts and mechanisms of both inductive and capacitive coupling on different filter structures are understood. Characterization methodology including measuring, modeling, and prediction of filter insertion loss is proposed. Mitigation solutions are proposed to reduce inter-component coupling and self-parasitics