173,902 research outputs found
Temperature Variation Operation of Mixed-VT 3T GC-eDRAM for Low Power Applications in 2Kbit Memory Array
Embedded memories were once utilized to transfer information between the CPU and the main memory. The cache storage in most traditional computers was static-random-access-memory (SRAM). Other memory technologies, such as embedded dynamic random-access memory (eDRAM) and spin-transfer-torque random-access memory (STT-RAM), have also been used to store cache data. The SRAM, on the other hand, has a low density and severe leakage issues, and the STT-RAM has high latency and energy consumption when writing. The gain-cell eDRAM (GC-eDRAM), which has a higher density, lower leakage, logic compatibility, and is appropriate for two-port operations, is an attractive option. To speed up data retrieval from the main memory, future processors will require larger and faster-embedded memories. Area overhead, power overhead, and speed performance are all issues with the existing architecture. A unique mixed-V_T 3T GC-eDRAM architecture is suggested in this paper to improve data retention times (DRT) and performance for better energy efficiency in embedded memories. The GC-eDRAM is simulated using a standard complementary-metal-oxide-semiconductor (CMOS) with a 130nm technology node transistor. The performance of a 2kbit mixed-V_T 3T GC-eDRAM array were evaluated through corner process simulations. Each memory block is designed and simulated using Mentor Graphics Software. The array, which is based on the suggested bit-cell, has been successfully operated at 400Mhz under a 1V supply and takes up almost 60-75% less space than 6T SRAM using the same technology. When compared to the existing 6T and 4T ULP SRAMs (others' work), the retention power of the proposed GC-eDRAM is around 80-90% lower
Fast, predictable and low energy memory references through architecture-aware compilation
The design of future high-performance embedded systems is hampered
by two problems: First, the required hardware needs more energy than is
available from batteries. Second, current cache-based approaches for bridging the
increasing speed gap between processors and memories cannot guarantee predictable
real-time behavior. A contribution to solving both problems is made in
this paper which describes a comprehensive set of algorithms that can be applied
at design time in order to maximally exploit scratch pad memories (SPMs). We
show that both the energy consumption as well as the computed worst case execution
time (WCET) can be reduced by up to to 80% and 48%, respectively, by
establishing a strong link between the memory architecture and the compiler
The narrative self, distributed memory, and evocative objects
In this article, I outline various ways in which artifacts are interwoven with autobiographical memory systems and conceptualize what this implies for the self. I first sketch the narrative approach to the self, arguing that who we are as persons is essentially our (unfolding) life story, which, in turn, determines our present beliefs and desires, but also directs our future goals and actions. I then argue that our autobiographical memory is partly anchored in our embodied interactions with an ecology of artifacts in our environment. Lifelogs, photos, videos, journals, diaries, souvenirs, jewelry, books, works of art, and many other meaningful objects trigger and sometimes constitute emotionally-laden autobiographical memories. Autobiographical memory is thus distributed across embodied agents and various environmental structures. To defend this claim, I draw on and integrate distributed cognition theory and empirical research in human-technology interaction. Based on this, I conclude that the self is neither defined by psychological states realized by the brain nor by biological states realized by the organism, but should be seen as a distributed and relational construct
Flash-memories in Space Applications: Trends and Challenges
Nowadays space applications are provided with a processing power absolutely overcoming the one available just a few years ago. Typical mission-critical space system applications include also the issue of solid-state recorder(s). Flash-memories are nonvolatile, shock-resistant and power-economic, but in turn have different drawbacks. A solid-state recorder for space applications should satisfy many different constraints especially because of the issues related to radiations: proper countermeasures are needed, together with EDAC and testing techniques in order to improve the dependability of the whole system. Different and quite often contrasting dimensions need to be explored during the design of a flash-memory based solid- state recorder. In particular, we shall explore the most important flash-memory design dimensions and trade-offs to tackle during the design of flash-based hard disks for space application
Memory ecologies
The individual and collective and also cultural domains have long constituted challenging boundaries for the study of memory. These are often clearly demarcated between approaches drawn from the human and the social sciences and also humanities, respectively. But recent work turns the enduring imagination â the world view â of these domains on its head by treating memory as serving a link between both the individual and collective past and future. Here, I employ some of the contributions from Schacter and Welkerâs Special Issue of Memory Studies on âMemory and Connectionâ to offer an âexpanded viewâ of memory that sees remembering and forgetting as the outcome of interactional trajectories of experience, both emergent and predisposed
A Cache Management Strategy to Replace Wear Leveling Techniques for Embedded Flash Memory
Prices of NAND flash memories are falling drastically due to market growth
and fabrication process mastering while research efforts from a technological
point of view in terms of endurance and density are very active. NAND flash
memories are becoming the most important storage media in mobile computing and
tend to be less confined to this area. The major constraint of such a
technology is the limited number of possible erase operations per block which
tend to quickly provoke memory wear out. To cope with this issue,
state-of-the-art solutions implement wear leveling policies to level the wear
out of the memory and so increase its lifetime. These policies are integrated
into the Flash Translation Layer (FTL) and greatly contribute in decreasing the
write performance. In this paper, we propose to reduce the flash memory wear
out problem and improve its performance by absorbing the erase operations
throughout a dual cache system replacing FTL wear leveling and garbage
collection services. We justify this idea by proposing a first performance
evaluation of an exclusively cache based system for embedded flash memories.
Unlike wear leveling schemes, the proposed cache solution reduces the total
number of erase operations reported on the media by absorbing them in the cache
for workloads expressing a minimal global sequential rate.Comment: Ce papier a obtenu le "Best Paper Award" dans le "Computer System
track" nombre de page: 8; International Symposium on Performance Evaluation
of Computer & Telecommunication Systems, La Haye : Netherlands (2011
Energy Saving Techniques for Phase Change Memory (PCM)
In recent years, the energy consumption of computing systems has increased
and a large fraction of this energy is consumed in main memory. Towards this,
researchers have proposed use of non-volatile memory, such as phase change
memory (PCM), which has low read latency and power; and nearly zero leakage
power. However, the write latency and power of PCM are very high and this,
along with limited write endurance of PCM present significant challenges in
enabling wide-spread adoption of PCM. To address this, several
architecture-level techniques have been proposed. In this report, we review
several techniques to manage power consumption of PCM. We also classify these
techniques based on their characteristics to provide insights into them. The
aim of this work is encourage researchers to propose even better techniques for
improving energy efficiency of PCM based main memory.Comment: Survey, phase change RAM (PCRAM
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