16,974 research outputs found
A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS
© 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio
A Built-In-Test Circuit for Functional Verification & PVT Variations Monitoring of CMOS RF Circuits
Built-In-Test (BIT) for Radio Frequency (RF) integrated circuits can reduce
the testing cost, especially with the increase of integration level and operating frequency.
A fully integrated CMOS BIT detection circuit is presented in this work. This BIT
detection circuit is rectifier-based and low threshold voltage diode-connected MOS
transistor with substrate positively-biased is used to improve the detecting sensitivity.
As an example, a 2.4GHz LNA is used, the high frequency small signal gain is extracted
and the gain fluctuation due to Process, supply Voltage and Temperature (PVT)
variations is also investigated. The simulation results show that this BIT detection
circuit can realize on-chip functional verification of RF circuits and also monitor the
influence of PVT variations on the performance of the circuit without affecting the high
frequency performance of the measured RF circuits
An In Depth Study into Using EMI Signatures for Appliance Identification
Energy conservation is a key factor towards long term energy sustainability.
Real-time end user energy feedback, using disaggregated electric load
composition, can play a pivotal role in motivating consumers towards energy
conservation. Recent works have explored using high frequency conducted
electromagnetic interference (EMI) on power lines as a single point sensing
parameter for monitoring common home appliances. However, key questions
regarding the reliability and feasibility of using EMI signatures for
non-intrusive load monitoring over multiple appliances across different sensing
paradigms remain unanswered. This work presents some of the key challenges
towards using EMI as a unique and time invariant feature for load
disaggregation. In-depth empirical evaluations of a large number of appliances
in different sensing configurations are carried out, in both laboratory and
real world settings. Insights into the effects of external parameters such as
line impedance, background noise and appliance coupling on the EMI behavior of
an appliance are realized through simulations and measurements. A generic
approach for simulating the EMI behavior of an appliance that can then be used
to do a detailed analysis of real world phenomenology is presented. The
simulation approach is validated with EMI data from a router. Our EMI dataset -
High Frequency EMI Dataset (HFED) is also released
Deep Space Network information system architecture study
The purpose of this article is to describe an architecture for the Deep Space Network (DSN) information system in the years 2000-2010 and to provide guidelines for its evolution during the 1990s. The study scope is defined to be from the front-end areas at the antennas to the end users (spacecraft teams, principal investigators, archival storage systems, and non-NASA partners). The architectural vision provides guidance for major DSN implementation efforts during the next decade. A strong motivation for the study is an expected dramatic improvement in information-systems technologies, such as the following: computer processing, automation technology (including knowledge-based systems), networking and data transport, software and hardware engineering, and human-interface technology. The proposed Ground Information System has the following major features: unified architecture from the front-end area to the end user; open-systems standards to achieve interoperability; DSN production of level 0 data; delivery of level 0 data from the Deep Space Communications Complex, if desired; dedicated telemetry processors for each receiver; security against unauthorized access and errors; and highly automated monitor and control
Communication system for a tooth-mounted RF sensor used for continuous monitoring of nutrient intake
In this Thesis, the communication system of a wearable device that monitors the user’s diet is studied. Based in a novel RF metamaterial-based mouth sensor, different decisions have to be made concerning the system’s technologies, such as the power source options for the device, the wireless technology used for communications and the method to obtain data from the sensor. These issues, along with other safety rules and regulations, are reviewed, as the first stage of development of the Food-Intake Monitoring projectOutgoin
System-level design and RF front-end implementation for a 3-10ghz multiband-ofdm ultrawideband receiver and built-in testing techniques for analog and rf integrated circuits
This work consists of two main parts: a) Design of a 3-10GHz UltraWideBand
(UWB) Receiver and b) Built-In Testing Techniques (BIT) for Analog and RF circuits.
The MultiBand OFDM (MB-OFDM) proposal for UWB communications has
received significant attention for the implementation of very high data rate (up to
480Mb/s) wireless devices. A wideband LNA with a tunable notch filter, a downconversion
quadrature mixer, and the overall radio system-level design are proposed for
an 11-band 3.4-10.3GHz direct conversion receiver for MB-OFDM UWB implemented
in a 0.25mm BiCMOS process. The packaged IC includes an RF front-end with
interference rejection at 5.25GHz, a frequency synthesizer generating 11 carrier tones in
quadrature with fast hopping, and a linear phase baseband section with 42dB of gain
programmability. The receiver IC mounted on a FR-4 substrate provides a maximum
gain of 67-78dB and NF of 5-10dB across all bands while consuming 114mA from a
2.5V supply.
Two BIT techniques for analog and RF circuits are developed. The goal is to reduce
the test cost by reducing the use of analog instrumentation. An integrated frequency response characterization system with a digital interface is proposed to test the
magnitude and phase responses at different nodes of an analog circuit. A complete
prototype in CMOS 0.35mm technology employs only 0.3mm2 of area. Its operation is
demonstrated by performing frequency response measurements in a range of 1 to
130MHz on 2 analog filters integrated on the same chip. A very compact CMOS RF
RMS Detector and a methodology for its use in the built-in measurement of the gain and
1dB compression point of RF circuits are proposed to address the problem of on-chip
testing at RF frequencies. The proposed device generates a DC voltage proportional to
the RMS voltage amplitude of an RF signal. A design in CMOS 0.35mm technology
presents and input capacitance <15fF and occupies and area of 0.03mm2. The application
of these two techniques in combination with a loop-back test architecture significantly
enhances the testability of a wireless transceiver system
- …