Finite worldlength effects in fixed-point implementations of linear systems

Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.Includes bibliographical references (p. 173-194).by Vinay Mohta.M.Eng

Strategies for neural networks in ballistocardiography with a view towards hardware implementation

A thesis submitted for the degree of Doctor of Philosophy at the University of LutonThe work described in this thesis is based on the results of a clinical trial conducted by the research team at the Medical Informatics Unit of the University of Cambridge, which show that the Ballistocardiogram (BCG) has prognostic value in detecting impaired left ventricular function before it becomes clinically overt as myocardial infarction leading to sudden death. The objective of this study is to develop and demonstrate a framework for realising an on-line BCG signal classification model in a portable device that would have the potential to find pathological signs as early as possible for home health care. Two new on-line automatic BeG classification models for time domain BeG classification are proposed. Both systems are based on a two stage process: input feature extraction followed by a neural classifier. One system uses a principal component analysis neural network, and the other a discrete wavelet transform, to reduce the input dimensionality. Results of the classification, dimensionality reduction, and comparison are presented. It is indicated that the combined wavelet transform and MLP system has a more reliable performance than the combined neural networks system, in situations where the data available to determine the network parameters is limited. Moreover, the wavelet transfonn requires no prior knowledge of the statistical distribution of data samples and the computation complexity and training time are reduced. Overall, a methodology for realising an automatic BeG classification system for a portable instrument is presented. A fully paralJel neural network design for a low cost platform using field programmable gate arrays (Xilinx's XC4000 series) is explored. This addresses the potential speed requirements in the biomedical signal processing field. It also demonstrates a flexible hardware design approach so that an instrument's parameters can be updated as data expands with time. To reduce the hardware design complexity and to increase the system performance, a hybrid learning algorithm using random optimisation and the backpropagation rule is developed to achieve an efficient weight update mechanism in low weight precision learning. The simulation results show that the hybrid learning algorithm is effective in solving the network paralysis problem and the convergence is much faster than by the standard backpropagation rule. The hidden and output layer nodes have been mapped on Xilinx FPGAs with automatic placement and routing tools. The static time analysis results suggests that the proposed network implementation could generate 2.7 billion connections per second performance

The development of a novel modem structure for connection of rural to diginet

Includes bibliographical references.This thesis investigates the use of partial response signalling as a modulation scheme in a modem structure. The modem structure consists of transmitter modulation and receiver demodulation sections only. The modem is designed to operate at data rates of 2400, 4800 and 9600 bps. The signalling format replaces the CCITT Recommendation V.29 format. The transmitted signal is required to conform to the bandwidth limitations of CCITT Recommendation M.1020 leased telephone circuits

Hardware Implementation Of Tunable Heterodyne Band-Pass Filters

Modem wireless and satellite communication systems make use of spreadspectrum modulation concepts such as Frequency-hopping spread-spectrum (FHSS) and Direct sequence spread-spectrum (DSSS). The spread-spectrum modulation method inherently possesses anti-jamming and anti-interception properties due to the fact that the narrowband information signal is spread over a wide range of frequencies, masking the information-bearing signal as noise. Despite these properties, these communication channels can be severely corrupted by high-powered narrowband interference signals generated by local FM or AM transmitters which may cause complications when detecting the information signal at the receiver. Therefore, the communication system is made more efficient with the use of signal processing techniques for narrowband interference attenuation. Control systems is another area where the presence of narrowband interference signal due to mechanical resonance can be responsible for causing distortion in information signal. Any Band-pass, High-pass or a Low-pass filter may be converted into a tunable filter through the use of new Tunable Heterodyne Band-pass Filter concept in which the frequency of the heterodyne signal is adjusted thereby creating the effect of translating the entire transfer function of the fixed filter in frequency. In this thesis, hardware implementation techniques and results of the new Digital Tunable Heterodyne Band-pass filter is proposed that allows a prototype IIR or FIR filter to be shifted through the entire range of digital frequencies with a single parameter, the heterodyning frequency. The unique property of this new tunable filter is the range of tunability it possesses. With this technique, the fixed filter is tuned continuously using the concept of frequency translation. The images created by the heterodyne process are cancelled without the use of image canceling filters, which significantly contribute towards a hardware efficient design. In this thesis, simulation results are observed to illustrate the effects ofhaving the fixed prototype filter as a band-pass, high-pass, low-pass or notch filter. This thesis concentrates on the hardware implementation of the tunable heterodyne filter structure with a band-pass filter as the fixed prototype filter. Thus, simulation and experimental results show that if the fixed filter is a narrowband Bandpass filter, a much hardware efficient implementation can be achieved by using the new Tunable Heterodyne Band-pass filter to extract the narrowband interference from broadband communication or control systems as compared to the standard techniques used. The proposed heterodyne filter is suitable both as a tunable filter or to be implemented with standard algorithms to design adaptive digital filters. The new structure proposed is composed of three main components which can be implemented using Field Programmable Gate Arrays (FPGA) or easily be retargeted for an Application Specific Integrated Circuits (ASIC) standard cell technology or custom designed for Very Large Scale Integration (VLSI) processes. A prototype system is implemented using a single chip Xilinx Virtex Series Field Programmable Gate Arrays (FPGA) and thesimulation results are compared with the hardware data

Feasibility of a 16bit, 3MSPS multibit per stage pipeline ADC using digital calibration

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science; and, Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1988.Includes bibliographical references (p. 115-116).by Matthew Louis Courcy.B.S.M.Eng