High compression image and image sequence coding

The digital representation of an image requires a very large number of bits. This number is even larger for an image sequence. The goal of image coding is to reduce this number, as much as possible, and reconstruct a faithful duplicate of the original picture or image sequence. Early efforts in image coding, solely guided by information theory, led to a plethora of methods. The compression ratio reached a plateau around 10:1 a couple of years ago. Recent progress in the study of the brain mechanism of vision and scene analysis has opened new vistas in picture coding. Directional sensitivity of the neurones in the visual pathway combined with the separate processing of contours and textures has led to a new class of coding methods capable of achieving compression ratios as high as 100:1 for images and around 300:1 for image sequences. Recent progress on some of the main avenues of object-based methods is presented. These second generation techniques make use of contour-texture modeling, new results in neurophysiology and psychophysics and scene analysis

Mining Fix Patterns for FindBugs Violations

In this paper, we first collect and track a large number of fixed and unfixed violations across revisions of software. The empirical analyses reveal that there are discrepancies in the distributions of violations that are detected and those that are fixed, in terms of occurrences, spread and categories, which can provide insights into prioritizing violations. To automatically identify patterns in violations and their fixes, we propose an approach that utilizes convolutional neural networks to learn features and clustering to regroup similar instances. We then evaluate the usefulness of the identified fix patterns by applying them to unfixed violations. The results show that developers will accept and merge a majority (69/116) of fixes generated from the inferred fix patterns. It is also noteworthy that the yielded patterns are applicable to four real bugs in the Defects4J major benchmark for software testing and automated repair.Comment: Accepted for IEEE Transactions on Software Engineerin

ARM2GC: Succinct Garbled Processor for Secure Computation

We present ARM2GC, a novel secure computation framework based on Yao's Garbled Circuit (GC) protocol and the ARM processor. It allows users to develop privacy-preserving applications using standard high-level programming languages (e.g., C) and compile them using off-the-shelf ARM compilers (e.g., gcc-arm). The main enabler of this framework is the introduction of SkipGate, an algorithm that dynamically omits the communication and encryption cost of the gates whose outputs are independent of the private data. SkipGate greatly enhances the performance of ARM2GC by omitting costs of the gates associated with the instructions of the compiled binary, which is known by both parties involved in the computation. Our evaluation on benchmark functions demonstrates that ARM2GC not only outperforms the current GC frameworks that support high-level languages, it also achieves efficiency comparable to the best prior solutions based on hardware description languages. Moreover, in contrast to previous high-level frameworks with domain-specific languages and customized compilers, ARM2GC relies on standard ARM compiler which is rigorously verified and supports programs written in the standard syntax.Comment: 13 page

Fault-tolerant computer study

A set of building block circuits is described which can be used with commercially available microprocessors and memories to implement fault tolerant distributed computer systems. Each building block circuit is intended for VLSI implementation as a single chip. Several building blocks and associated processor and memory chips form a self checking computer module with self contained input output and interfaces to redundant communications buses. Fault tolerance is achieved by connecting self checking computer modules into a redundant network in which backup buses and computer modules are provided to circumvent failures. The requirements and design methodology which led to the definition of the building block circuits are discussed

Static Trace-Based Deadlock Analysis for Synchronous Mini-Go

We consider the problem of static deadlock detection for programs in the Go programming language which make use of synchronous channel communications. In our analysis, regular expressions extended with a fork operator capture the communication behavior of a program. Starting from a simple criterion that characterizes traces of deadlock-free programs, we develop automata-based methods to check for deadlock-freedom. The approach is implemented and evaluated with a series of examples

A Stacking-Based Misbehavior Detection System in Vehicular Communication Networks

Over the past few decades communication systems for vehicles have continued to advance. Communications between these vehicles can be classified into safety related and non safety related messages. An example of a safety related message would be one vehicle warning others of an icy road it encountered, where a non safety related communication would be a passenger streaming a movie. In either case it\u27s important to secure the communications so that the system continues to behave as expected. In this thesis we propose a Misbehavior Detection System (MDS), which is a system that monitors messages sent between vehicles, and detects misbehaviors for possible attacks. In our approach we use a stacking based machine learning algorithm to determine if vehicles are misbehaving. We then compare this approach to other MDS to determine if our approach makes a measurable difference. In the analysis and comparison section of this thesis, we evaluate the simulation and performance data, showing that our protocol has an accuracy of 91.8%. Advisor: Yi Qia

A Hybrid Scheme based on Alternative Scalar Leader Election (HS-ASLE) for Redundant Data Minimization in Multi-event Occurrence Scenario for WMSNs

The current paper reports a hybrid approach namely “Hybrid Scheme based on Alternative Scalar Leader Election (HS-ASLE)” for camera sensor actuation in multi-event occurrence scenario. In the proposed approach, the whole monitored zone gets segregated into multiple virtual sub-compartments and in each of the sub-compartments, one and three scalar leaders are elected alternatively that behave as the representatives of scalars to report event information. During the event occurrence, the event information gets trapped through the scalar leaders in lieu of scalars and the leaders convey the event occurrence information to the respective camera sensors. Pervasive experiment and observation have been ordained to mark the impact of varying the number of deployed scalar sensors and camera sensors individually on various performance parameters in multi-event occurrence ambience. Further, the numerical outcomes attained in terms of number of cameras actuated, coverage ratio, redundance ratio and energy expenditure for camera activation proclaim the effectiveness of our proposed HS-ASLE over the other two existing approaches in literature. Moreover, it is marked that our proposed approach attains maximal event region coverage with least camera activation, least redundant data transmission and lowest energy expenditure for camera sensor actuation as compared to two other approaches, which justify the precedence of our proposition over the other existing approaches