Run-time Support for Distributed Sharing in Typed Languages

We present a new run-time system, DOSA, that efficiently implements a shared object space abstraction underneath a typed programming language. The key insight behind DOSA is that the ability to unambiguously distinguish pointers from data at run-time enables efficient fine-grained sharing using VM support. Like earlier systems designed for fine-grained sharing, DOSA improves the performance of fine-grained applications by eliminating false sharing. In contrast to these earlier systems, DOSA's VM-based approach and read aggregation enable it to match a page-based system on coarse-grained applications. Furthermore, its architecture permits optimizations that are not possible in conventional fine-grained or coarse-grained DSM systems

Ozone: Efficient Execution with Zero Timing Leakage for Modern Microarchitectures

Time variation during program execution can leak sensitive information. Time variations due to program control flow and hardware resource contention have been used to steal encryption keys in cipher implementations such as AES and RSA. A number of approaches to mitigate timing-based side-channel attacks have been proposed including cache partitioning, control-flow obfuscation and injecting timing noise into the outputs of code. While these techniques make timing-based side-channel attacks more difficult, they do not eliminate the risks. Prior techniques are either too specific or too expensive, and all leave remnants of the original timing side channel for later attackers to attempt to exploit. In this work, we show that the state-of-the-art techniques in timing side-channel protection, which limit timing leakage but do not eliminate it, still have significant vulnerabilities to timing-based side-channel attacks. To provide a means for total protection from timing-based side-channel attacks, we develop Ozone, the first zero timing leakage execution resource for a modern microarchitecture. Code in Ozone execute under a special hardware thread that gains exclusive access to a single core's resources for a fixed (and limited) number of cycles during which it cannot be interrupted. Memory access under Ozone thread execution is limited to a fixed size uncached scratchpad memory, and all Ozone threads begin execution with a known fixed microarchitectural state. We evaluate Ozone using a number of security sensitive kernels that have previously been targets of timing side-channel attacks, and show that Ozone eliminates timing leakage with minimal performance overhead

On the Usage of Geolocation-Aware Spectrum Measurements for Incumbent Location and Transmit Power Detection

© 2017 IEEE. Determining the geographical area that needs to be excluded due to incumbent activity is critical to realize high spectral utilization in spectrum sharing networks. This can be achieved by estimating the incumbent location and transmit power. However, keeping the hardware complexity of sensing nodes to a minimum and scalability are critical for spectrum sharing applications with commercial intent. We present a discrete-space l1-norm minimization solution based on geolocation-aware energy detection measurements. In practice, the accuracy of geolocation tagging is limited. We capture the impact as a basis mismatch and derive the necessary condition that needs to be satisfied for successful detection of multiple incumbents' location and transmit power. We find the upper bound for the probability of eliminating the impact of limited geolocation tagging accuracy in a lognormal shadow fading environment, which is applicable to all generic I1-norm minimization techniques. We propose an algorithm based on orthogonal matching pursuit that decreases the residual in each iteration by allowing a selected set of basis vectors to rotate in a controlled manner. Numerical evaluation of the proposed algorithm in a Licensed Shared Access (LSA) network shows a significant improvement in the probability of missed detection and false alarm

Finding regulatory modules through large-scale gene-expression data analysis

The use of gene microchips has enabled a rapid accumulation of gene-expression data. One of the major challenges of analyzing this data is the diversity, in both size and signal strength, of the various modules in the gene regulatory networks of organisms. Based on the Iterative Signature Algorithm [Bergmann, S., Ihmels, J. and Barkai, N. (2002) Phys. Rev. E 67, 031902], we present an algorithm - the Progressive Iterative Signature Algorithm (PISA) - that, by sequentially eliminating modules, allows unsupervised identification of both large and small regulatory modules. We applied PISA to a large set of yeast gene-expression data, and, using the Gene Ontology annotation database as a reference, found that our algorithm is much better able to identify regulatory modules than methods based on high-throughput transcription-factor binding experiments or on comparative genomics.Comment: 7 pages, 6 figures in main text; 2 text pages, 7 figures, 1 table in supplement; rewritten versio

Implementing Groundness Analysis with Definite Boolean Functions

The domain of definite Boolean functions, Def, can be used to express the groundness of, and trace grounding dependencies between, program variables in (constraint) logic programs. In this paper, previously unexploited computational properties of Def are utilised to develop an efficient and succinct groundness analyser that can be coded in Prolog. In particular, entailment checking is used to prevent unnecessary least upper bound calculations. It is also demonstrated that join can be defined in terms of other operations, thereby eliminating code and removing the need for preprocessing formulae to a normal form. This saves space and time. Furthermore, the join can be adapted to straightforwardly implement the downward closure operator that arises in set sharing analyses. Experimental results indicate that the new Def implementation gives favourable results in comparison with BDD-based groundness analyses

Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery

The trend of downsizing transistors and operating voltage scaling has made the processor chip more sensitive against radiation phenomena making soft errors an important challenge. New reliability techniques for handling soft errors in the logic and memories that allow meeting the desired failures-in-time (FIT) target are key to keep harnessing the benefits of Moore's law. The failure to scale the soft error rate caused by particle strikes, may soon limit the total number of cores that one may have running at the same time. This paper proposes a light-weight and scalable architecture to eliminate silent data corruption errors (SDC) and detected unrecoverable errors (DUE) of a core. The architecture uses acoustic wave detectors for error detection. We propose to recover by confining the errors in the cache hierarchy, allowing us to deal with the relatively long detection latencies. Our results show that the proposed mechanism protects the whole core (logic, latches and memory arrays) incurring performance overhead as low as 0.60%. © 2014 IEEE.Peer ReviewedPostprint (author's final draft