Impact of Strain on the Performance of Si Nanowires Transistors at the Scaling Limit: A 3D Monte Carlo/2D Poisson Schrodinger Simulation Study

In this work we investigate the correlation between channel strain and device performance in various n-type Si-NWTs. We establish a correlation between strain, gate length and cross-section dimension of the transistors. For the purpose of this paper we simulate Si NWTs with a <110> channel orientation, four different ellipsoidal channel cross-sections and five gate lengths: 4nm, 6nm, 8nm, 10nm and 12nm. We have also analyzed the impact of strain on drain-induced barrier lowering (DIBL) and the subthreshold slope (SS). All simulations are based on a quantum mechanical description of the mobile charge distribution in the channel obtained from a 2D solution of the Schrödinger equation in multiple cross sections along the current path, which is mandatory for nanowires with such ultra-scale dimensions. The current transport along the channel is simulated using 3D Monte Carlo (MC) and drift-diffusion (DD) approaches

A Backscattering Model Incorporating the Effective Carrier Temperature in Nano MOSFET

In this work we propose a channel backscattering model in which increased carrier temperature at the top of the potential energy barrier in the channel is taken into account. This model represents an extension of a previous model by the same authors which highlighted the importance of considering the partially ballistic transport between the source contact and the top of the potential energy barrier in the channel. The increase of carrier temperature is precisely due to energy dissipation between the source contact and the top of the barrier caused by the high saturation current. To support our discussion, accurate 2D full band Monte Carlo device simulations with quantum correction have been performed in double gate nMOSFETs for different geometries (gate length down to 10 nm), biases and lattice temperatures. Including the effective carrier temperature is especially important to properly treat the high inversion regime, where previous backscattering models usually fail

Breakdown of universal mobility curves in sub-100-nm MOSFETs

We explore the breakdown of universal mobility behavior in sub-100-nm Si MOSFETs, using a novel three-dimensional (3-D) statistical simulation approach. In this approach, carrier trajectories in the bulk are treated via 3-D Brownian dynamics, while the carrier-interface roughness scattering is treated using a novel empirical model

Diffusive Transport in Quasi-2D and Quasi-1D Electron Systems

Quantum-confined semiconductor structures are the cornerstone of modern-day electronics. Spatial confinement in these structures leads to formation of discrete low-dimensional subbands. At room temperature, carriers transfer among different states due to efficient scattering with phonons, charged impurities, surface roughness and other electrons, so transport is scattering-limited (diffusive) and well described by the Boltzmann transport equation. In this review, we present the theoretical framework used for the description and simulation of diffusive electron transport in quasi-two-dimensional and quasi-one-dimensional semiconductor structures. Transport in silicon MOSFETs and nanowires is presented in detail.Comment: Review article, to appear in Journal of Computational and Theoretical Nanoscienc

Efficient hole transport model in warped bands for use in the simulation of Si/SiGe MOSFETs

An analytical geometric model for the valence band in strained and relaxed Si1-xGex is presented, which shows good agreement with a 6-band k·p analysis of the valence band. The geometric model allows us to define an effective mass tensor for the warped valence band structure. The model also has applications in the study of III-V semiconductors, and could aid in the interpretation of cyclotron resonance experiments in these bands. A warped three-band Monte Carlo simulation has been developed based on this model making use of the efficient calculation of trajectory dynamics that is made possible through the use of such a model. The calculated transport characteristics show good agreement with the available experimental data

Monte Carlo study of current variability in UTB SOI DG MOSFETs

The scaling of conventional silicon based MOSFETs is increasingly difficult into the nanometer regime due to short channel effects, tunneling and subthreshold leakage current. Ultra-thin body silicon-on-insulator based architectures offer a promising alternative, alleviating these problems through their geometry. However, the transport behaviour in these devices is more complex, especially for silicon thicknesses below 10 nm, with enhancement from band splitting and volume inversion competing with scattering from phonons, Coulomb interactions, interface roughness and body thickness fluctuation. Here, the effect of the last scattering mechanism on the drive current is examined as it is considered a significant limitation to device performance for body thicknesses below 5 nm. A simulation technique that properly captures non-equilibrium transport, includes quantum effects and maintains computational efficiency is essential for the study of this scattering mechanism. Therefore, a 3D Monte Carlo simulator has been developed which includes this scattering effect in an ab initio fashion, and quantum corrections using the Density Gradient formalism. Monte Carlo simulations using `frozen field' approximation have been carried out to examine the dependence of mobility on silicon thickness in large, self averaging devices. This approximation is then used to carry out statistical studies of uniquely different devices to examine the variability of on-current. Finally, Monte Carlo simulations self consistent with Poisson's equation have been carried out to further investigate this mechanism