Scaling and process effect on electromigration reliability for Cu/low k interconnects

textThe microelectronics industry has been managing the RC delay problem arising from aggressive line scaling, by replacing aluminum (Al) by copper (Cu) and oxide dielectric by low-k dielectric. Electromigration (EM) turned out to be a serious reliability problem for Cu interconnects due to the implementation of mechanically weaker low-k dielectrics. In addition, line width and via size scaling resulted in the need of a novel diffusion barrier, which should be uniform and thin. The objective of this dissertation is to investigate the impacts of Ta barrier process, such as barrier-first and pre-clean first, and scaling of barrier and line/via on EM reliability of Cu/low-k interconnects. For this purpose, EM statistical test structures, having different number of line segments, line width, and via width, were designed. The EM test structures were fabricated by a dualdamascene process with two metal layers (M1/Via/M2), which were then packaged for EM tests. The package-level EM tests were performed in a specially designed vacuum chamber with pure nitrogen environment. The novel barrier deposition process, called barrier-first, showed a higher (jL)[subscript c] product and prolonged EM lifetime, compared with the conventional Ta barrier deposition process, known as pre-clean first. This can be attributed to the improved uniformity and thickness of the Ta layer on the via and trench, as confirmed by TEM. As for the barrier thickness effect, the (jL)c product decreased with decreasing thickness, due to reduced Cu confinement. A direct correlation between via size and EM reliability was found; namely, EM lifetime and statistics degraded with via size. This can be attributed to the fact that critical void length to cause open circuit is about the size of via width. To investigate further line scaling effect on EM reliability, SiON (siliconoxynitride) trenchfilling process was introduced to fabricate 60-nm lines, corresponding to 45-nm technology, using a conventional, wider line lithograph technology. The EM lifetime of 60-nm fine lines with SiON filling was longer than that of a standard damascene structure, which can be attributed to a distinct via/metal-1 configuration in reducing process-induced defects at the via/metal-1 interface.Materials Science and Engineerin

Preparation and characterization of Carbon Nanotube based vertical interconnections for integrated circuits: Preparation and characterization of Carbon Nanotube based verticalinterconnections for integrated circuits

(ULSI) causes an increase of the resistance of the wiring system by increased scattering of electrons at side walls and grain boundaries in the state of the art Cu technology, which increases the RC delay of the interconnect system and thus degrades the performance of the device. The outstanding properties of carbon nanotubes (CNT) such as a large mean free path, a high thermal conductance and a large resistance against electromigration make them an ideal candidate to replace Cu in future feature nodes. The present thesis contributes to the preparation and properties of CNT based vertical interconnections (vias). In addition, all processes applied during the fabrication are compatible to ULSI and an interface between CNT based vias and a Cu metallization is studied. The methodology for the evaluation of CNT based vias is improved; it is highlighted that by measuring the resistance of one multiwall CNT and taking into account the CNT density, the performance of the CNT based vias can be predicted accurately. This provides the means for a systematic evaluation of different integration procedures and materials. The lowest contact resistance is obtained for carbide forming metals, as long as oxidation during the integration is avoided. Even though metal-nitrides exhibit an enhanced contact resistance, they are recommended to be used at the bottom metallization in order to minimize the oxidation of the metal-CNT contact during subsequent processing steps. Overall a ranking for the materials from the lowest to the highest contact resistance is obtained: Ta < Ti < TaN < TiN « TiO2 « Ta2O5 Furthermore the impact of post CNT growth procedures as chemical mechanical planarization, HF treatment and annealing procedures after the CNT based via fabrication are evaluated. The conductance of the incorporated CNTs and the applicable electrical transport regime relative to the CNT quality and the CNT length is discussed. In addition, a strong correlation between the temperature coefficient of resistance and the initial resistance of the CNT based vias at room temperature has been observed.Die kontinuierliche Miniaturisierung der charakteristischen Abmessungen in hochintegrierten Schaltungen (ULSI) verursacht einen Anstieg des Widerstandes im Zuleitungssystem aufgrund der erhöhten Streuung von Elektronen an Seitenwänden und Korngrenzen in der Cu-Technologie, wodurch die Verzögerungszeit des Zuleitungssystems ansteigt. Die herausragenden Eigenschaften von Kohlenstoffnanoröhren (CNT), wie eine große mittlere freie Weglänge, hohe thermische Leitfähigkeit und eine starke Resistenz gegenüber Elektromigration machen diese zu einem idealen Kandidaten, um Cu in zukünftigen Technologiegenerationen zu ersetzen. Die vorliegende Arbeit beschreibt die Herstellung und daraus resultierenden Eigenschaften von Zwischenebenenkontakten (Vias) basierend auf CNTs. Alle verwendeten Prozessierungsschritte sind kompatibel mit der Herstellung von hochintegrierten Schaltkreisen und eine Schnittstelle zwischen den CNT Vias und einer Cu-Metallisierung ist vorhanden. Insbesondere das Verfahren zur Evaluierung von CNT Vias wurde durch den Einsatz verschiedener Methoden verbessert. Insbesondere soll hervorgehoben werden, dass durch die Messung des Widerstandes eines einzelnen CNTs, bei bekannter CNT Dichte, der Via Widerstand sehr genau vorausgesagt werden kann. Dies ermöglicht eine systematische Untersuchung des Einflusses der verschiedenen Prozessschritte und der darin verwendeten Materialien auf den Via Widerstand. Der niedrigste Kontaktwiderstand wird für Karbidformierende Metalle erreicht, solange Oxidationsprozesse ausgeschlossen werden können. Obwohl Metallnitride einen höheren Kontaktwiderstand aufweisen, sind diese für die Unterseitenmetallisierung zu empfehlen, da dadurch die Oxidation der leitfähigen Schicht minimiert wird. Insgesamt kann eine Reihenfolge beginnend mit dem niedrigsten zum höchsten Kontaktwiderstand aufgestellt werden: Ta < Ti < TaN < TiN « TiO2 « Ta2O5 Desweiteren wurde der Einfluss von Verfahren nach dem CNTWachstum wie die chemischmechanische Planarisierung, eine HF Behandlung und einer Temperaturbehandlung evaluiert, sowie deren Einfluss auf die elektrischen Parameter des Vias untersucht. Die Leitfähigkeit der integrierten CNTs und die daraus resultierenden elektrischen Transporteigenschaften in Abhängigkeit der CNT Qualität und Länge werden besprochen. Ebenso wird die starke Korrelation zwischen dem Temperaturkoeffizienten des elektrischen Widerstandes und des Ausgangswiderstandes der CNT basierten Vias bei Raumtemperatur diskutiert

Caractérisation in operando de l’endommagement par électromigration des interconnexions 3D : Vers un modèle éléments finis prédictif

3D integration, conception mode of chips stacking, aims at both systems densification and functions diversification. The downsizing of 3D interconnects dimensions and the increase of current density rise the hazard related to electromigration. An accurate knowledge of the phenomenon is required to develop a predictive modeling of the failure in order to anticipate the difficulties as soon as the stage of technologies conception. Thus, a hitherto unseen SEM in operando observation method is devised. The test structure with “high density” through silicon vias (TSV) is tested at 350 °C with an injected current density of about 1 MA/cm², and simultaneously characterized. Regular shots of micrographs inform about the voids nucleation, forced in copper lines above the TSV, and about the scenario of their evolution. Islets formation and voids curing are also observed during the tens to hundreds hours of tests. A clear relation is established between voids evolution and the one of the electrical resistance. The different tests, completed by post-mortem analyses (FIB-SEM, EBSD, TEM), demonstrate the impact of microstructure on the depletion mechanism. Grains boundaries are preferential voids nucleation sites and influence the voids evolution. A probable effect of grains size and crystallographic orientation is revealed. Finally, the study focuses on the implementation of a multiphysics modeling in a finite elements code of the voids nucleation phase. This modeling is constituted of the main terms of the migration management.L'intégration 3D, mode de conception par empilement des puces, vise à la fois la densification des systèmes et la diversification des fonctions. La réduction des dimensions des interconnexions 3D et l'augmentation de la densité de courant accroissent les risques liés à l'électromigration. Une connaissance précise de ce phénomène est requise pour développer un modèle numérique prédictif de la défaillance et ainsi anticiper les difficultés dès le stade de la conception des technologies. Une méthode inédite d'observation in operando dans un MEB de l'endommagement par électromigration des interconnexions 3D est conçue. La structure d'étude avec des vias traversant le silicium (TSV) « haute densité » est testée à 350 °C avec une densité de courant injectée de l'ordre de 1 MA/cm², et simultanément caractérisée. La réalisation régulière de micrographies informe sur la nucléation des cavités, forcée dans la ligne de cuivre au-dessus des TSV, et sur le scénario de leur évolution. La formation d'ilots et la guérison des cavités sont également observées au cours des essais (quelques dizaines à centaines d'heures). Une relation claire est établie entre l'évolution des cavités et celle de la résistance électrique du dispositif. Les différents essais, complétés par des analyses post-mortem (FIB-SEM, EBSD, MET) démontrent l'impact de la microstructure sur le mécanisme de déplétion. Les joints de grains sont des lieux préférentiels de nucléation et influencent l'évolution des cavités. Un effet probable de la taille des grains et de leur orientation cristalline est également révélé. Enfin, l'étude se consacre à l'implémentation d'un modèle multiphysique dans un code éléments finis de la phase de nucléation des cavités. Ce modèle est constitué des principaux termes de gestion de la migration

Charakterisierung und Optimierung elektrochemisch abgeschiedener Kupferdünnschichtmetallisierungen für Leitbahnen höchstintegrierter Schaltkreise

Die Entwicklung der Mikroelektronik wird durch eine fortschreitende Miniaturisierung der Bauelemente geprägt. Infolge einer Reduzierung der Querschnittflächen von Leitbahnstrukturen erhöht sich die elektrische Leistungsdichte und das Metallisierungssystem bestimmt zunehmend die Übertragungsgeschwindigkeiten. Kupfer repräsentiert hierbei das verbreitetste Leitbahnmaterial und wird vorwiegend mittels elektrochemischer Abscheidung in vergrabene Damaszen-Strukturen eingebracht. Die vorliegende Dissertation beschreibt Möglichkeiten für eine Optimierung von Kupferleitbahnen für höchstintegrierte Schaltkreise. Von besonderem Interesse sind hierbei die Gefügequalität und der Reinheitsgrad. Es erfolgen umfangreiche werkstoffanalytische und elektrochemische Untersuchungen zur Charakterisierung von Depositionsmechanismen, des Einbaus von Fremdstoffen, des Mikrogefüges nach der Abscheidung und der Mikrogefügeumwandlung. In einem abschließenden Forschungsschwerpunkt werden Kupfer-Damaszen-Teststrukturen mit unterschiedlichen Gehalten nichtmetallischer Verunreinigungen hergestellt und entsprechenden Lebensdauerexperimenten unterzogen. Hierdurch gelingt eine Evaluierung des Einflusses jener Verunreinigungen auf die Elektromigrationsbeständigkeit von Kupferleitbahnen. Die Arbeit umfasst daher das gesamte Spektrum von der Grundlagenforschung bis zur Applikation von elektrochemisch abgeschiedenen Kupferdünnschichtmetallisierungen

Nanoscale III-V Semiconductor Photodetectors for High-Speed Optical Communications

Nanophotonics involves the study of the behavior of light on nanometer scale. Modern nanoscale semiconductor photodetectors are important building blocks for high-speed optical communications. In this chapter, we review the state-of-the-art 2.5G, 10G, and 25G avalanche photodiodes (APDs) that are available in commercial applications. We discuss the key device parameters, including avalanche breakdown voltage, dark current, temperature dependence, bandwidth, and sensitivity. We also present reliability analysis on wear-out degradation and optical/electrical overload stress. We discuss the reliability challenges of nanoscale photodetectors associated with device miniaturization for the future. The reliability aspects in terms of high electric field, Joule heating, and geometry inhomogeneity are highlighted

Analysis of Electromigration Behavior in Giant Magnetoresistance Spin Valve Read Sensors

Ph.DDOCTOR OF PHILOSOPH

Modeling of pattern dependencies in the fabrication of multilevel copper metallization

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2007.Includes bibliographical references (p. 295-303).Multilevel copper metallization for Ultra-Large-Scale-Integrated (ULSI) circuits is a critical technology needed to meet performance requirements for advanced interconnect technologies with sub-micron dimensions. It is well known that multilevel topography resulting from pattern dependencies in various processes, especially copper Electrochemical Deposition (ECD) and Chemical-Mechanical Planarization (CMP), is a major problem in interconnects. An integrated pattern dependent chip-scale model for multilevel copper metallization is contributed to help understand and meet dishing and erosion requirements, to optimize the combined plating and polishing process to achieve minimal environmental impact, higher yield and performance, and to enable optimization of layout and dummy fill designs. First, a physics-based chip-scale copper ECD model is developed. By considering copper ion depletion effects, and surface additive adsorption and desorption, the plating model is able to predict the initial topography for subsequent CMP modeling with sufficient accuracy and computational efficiency. Second, a compatible chip-scale CMP modeling is developed.(cont.) The CMP model integrates contact wear and density-step-height approaches, so that a consistent and coherent chip-scale model framework can be used for copper bulk polishing, copper over-polishing, and barrier layer polishing stages. A variant of this CMP model is developed which explicitly considers the pad topography properties. Finally, ECD and CMP parts are combined into an integrated model applicable to single level and multilevel metallization cases. The integrated multilevel copper metallization model is applied to the co-optimization of the plating and CMP processes. An alternative in-pattern (rather than between-pattern) dummy fill strategy is proposed. The integrated ECD/CMP model is applied to the optimization of the in-pattern fill, to achieve improved ECD uniformity and final post-CMP topography.by Hong Cai.Ph.D

Interconnects for future technology generations - conventional CMOS with copper/low-k and beyond

The limitations of the conventional Cu/low-k interconnect technology for use in future ultra-scaled integrated circuits down to 7 nm in the year 2020 are investigated from the power/performance point of view. Compact models are used to demonstrate the impacts of various interconnect process parameters, for instance, the interconnect barrier/liner bilayer thickness and aspect ratio, on the design and optimization of a multilevel interconnect network. A framework to perform a sensitivity analysis for the circuit behavior to interconnect process parameters is created for future FinFET CMOS technology nodes. Multiple predictive cell libraries down to the 7‒nm technology node are constructed to enable early investigation of the electronic chip performance using commercial electronic design automation (EDA) tools with real chip information. Findings indicated new opportunities that arise for emerging novel interconnect technologies from the materials and process perspectives. These opportunities are evaluated based on potential benefits that are quantified with rigorous circuit-level simulations and requirements for key parameters are underlined. The impacts of various emerging interconnect technologies on the performances of emerging devices are analyzed to quantify the realistic circuit- and system-level benefits that these new switches can offer.Ph.D

A hierarchical optimization engine for nanoelectronic systems using emerging device and interconnect technologies

A fast and efficient hierarchical optimization engine was developed to benchmark and optimize various emerging device and interconnect technologies and system-level innovations at the early design stage. As the semiconductor industry approaches sub-20nm technology nodes, both devices and interconnects are facing severe physical challenges. Many novel device and interconnect concepts and system integration techniques are proposed in the past decade to reinforce or even replace the conventional Si CMOS technology and Cu interconnects. To efficiently benchmark and optimize these emerging technologies, a validated system-level design methodology is developed based on the compact models from all hierarchies, starting from the bottom material-level, to the device- and interconnect-level, and to the top system-level models. Multiple design parameters across all hierarchies are co-optimized simultaneously to maximize the overall chip throughput instead of just the intrinsic delay or energy dissipation of the device or interconnect itself. This optimization is performed under various constraints such as the power dissipation, maximum temperature, die size area, power delivery noise, and yield. For the device benchmarking, novel graphen PN junction devices and InAs nanowire FETs are investigated for both high-performance and low-power applications. For the interconnect benchmarking, a novel local interconnect structure and hybrid Al-Cu interconnect architecture are proposed, and emerging multi-layer graphene interconnects are also investigated, and compared with the conventional Cu interconnects. For the system-level analyses, the benefits of the systems implemented with 3D integration and heterogeneous integration are analyzed. In addition, the impact of the power delivery noise and process variation for both devices and interconnects are quantified on the overall chip throughput.Ph.D