Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm

A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the combination of behavioral models for performance evaluation, optimization routines to minimize the power and area consumption of the circuit solution, and an algorithm to efficiently constraint the converter design space. This algorithm precludes the cost of lengthy bottom-up verifications and speeds up the synthesis task. The approach is herein demonstrated via the design of a 0.13 μm CMOS 10 bits@60 MS/s pipeline ADC with energy consumption per conversion of only 0.54 pJ@1 MHz, making it one of the most energy-efficient 10-bit video-rate pipeline ADCs reported to date. The computational cost of this design is of only 25 min of CPU time, and includes the evaluation of 13 different pipeline architectures potentially feasible for the targeted specifications. The optimum design derived from the synthesis procedure has been fine tuned to support PVT variations, laid out together with other auxiliary blocks, and fabricated. The experimental results show a power consumption of 23 [email protected] V and an effective resolution of 9.47-bit@1 MHz. Bearing in mind that no specific power reduction strategy has been applied; the mentioned results confirm the reliability of the proposed approach.Ministerio de Ciencia e Innovación TEC2009-08447Junta de Andalucía TIC-0281

Accurate Settling-Time Modeling and Design Procedures for Two-Stage Miller-Compensated Amplifiers for Switched-Capacitor Circuits

We present modeling techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with Miller-compensated operational transconductance amplifiers (OTAs). One distinctive feature of the proposal is the computation of the impact of signal levels (on both the model parameters and the model structure) as they change during transient evolution. This is achieved by using an event-driven behavioral approach that combines small- and large-signal behavioral descriptions and keeps track of the amplifier state after each clock phase. Also, SC circuits are modeled under closed-loop conditions to guarantee that the results remain close to those obtained by electrical simulation of the actual circuits. Based on these models, which can be regarded as intermediate between the more established small-signal approach and full-fledged simulations, design procedures for dimensioning SC building blocks are presented whose targets are system-level specifications (such as ENOB and SNDR) instead of OTA specifications. The proposed techniques allow to complete top-down model-based designs with 0.3-b accuracy.Ministerio de Educación y Ciencia TEC2006-03022Junta de Andalucía TIC-0281

Using behavioral modeling and simulation for learning communication circuits and systems

Comunicación presentada al "Global Engineering Education Conference (EDUCON)" celebrado en Marrakech (Marruecos) del 17 al 20 de Abril del 2012.This paper analyzes the use of behavioral simulation techniques to enhance the teaching-learning process in electrical engineering courses, specifically those dealing with circuits for communication systems. The method - which can be applied to both undergraduate and master courses - allows students to better understand complex circuit- and device-level phenomena, by describing them at a higher abstraction level. As a demonstration vehicle of the presented methodology, two examples are considered in this work: an analog front-end of a direct-conversion digital radio receiver and a ΣΔ modulator. In both cases, behavioral models of the different subcircuits have been implemented in MATLAB/SIMULINK and used by the students enrolled in two different courses: an undergraduate course and a master course. The results presented in this paper reveal that students become highly motivated and satisfied with the course contents and the proposed simulation-based learning methodology.This work has been supported in part by the Spanish Ministry of Science and Innovation (with support from the European Regional Development Fund) under contracts TEC2007-67247-C02-01/MIC, TEC2010-14825/MIC, in part by the Consejería de Innovación, Ciencia y Empresa, under contract TIC-2532 and in part by the I Plan Propio de Docencia de la U. de Sevilla, LabCMA2010 project.Peer Reviewe