780 research outputs found
Process development and reliability of thin gate oxides
The Semiconductor Industry Association\u27s (SIA) current National Technological Roadmap calls for the development of a suitable dielectric material for use in gate oxide for the 0.18|micrometers generation of chips and beyond. Some of the key challenges identified are resistance to oxide trapped charge generation from higher levels of tunneling currents and/or plasma processing, and formation of an effective barrier to dopant penetration during the gate processing. One promising material to meet these challenges is nitrided thermal oxide. Development of a growth process that yields high quality, lOnm thick, thermally grown Si02 films at RJT for use as a gate dielectric is described. Thin oxides (8nm - 20nm) were grown by thermal oxidation followed by inert anneals in Ar and N2. Nitrided oxides were created by implanting N2 (dose range: 5el3 - lei 5 /cm2) into the substrate prior to gate oxidation. Test equipment was setup to study Fowler Nordheim (FN) tunneling and dielectric breakdown. Test structures consisted of conventional and novel MOS capacitor structures with aluminum and poly-silicon gate electrodes. Scaling RJT\u27s existing, 20nm oxidation process to lOnm resulted in degradation of dielectric strength from \u3e lOMV/cm to ~6-7MV/cm for Al-gate MOS capacitors. Replacing the Al gate material with poly-silicon restored the dielectric strength to lOMV/cm. Performing an N2 implant through a screening oxide, prior to gate oxidation, was investigated as a means of obtaining a nitrided thermal oxide. For certain doses (5el3 - 5el4 /cm2), Al-gate MOS capacitors exhibited an improved dielectric strength as the mean value increased from 6- 7MV/cm to ~9MV/cm. Poly-Si gate MOS capacitors showed a similar improvement for the nitrided oxides, exhibiting mean dielectric strength values in the 10-12MV/cm range. Fowler- Nordheim (FN) tunnel current measurements showed that the nitrided films exhibit lower leakage levels and less charge trapping than their thermal Si02 counterparts. Results indicate that a 12nm nitrided oxide, for a certain dose (5el4/cm2), exhibited equivalent electrical performance to a 20nm thermally grown Si02 oxide. In conclusion, a process was developed for yielding reliable thin gate oxides (~10nm) in a university fab
Study of the effects of deuterium implantation upon the performance of thin-oxide CMOS devices
The use of ultra thin oxide films in modem semiconductor devices makes them increasingly susceptible to damage due to the hot carrier damage. Deuterium in place of hydrogen was introduced by ion implantation at the silicon oxide-silicon interface during fabrication to satisfy the dangling bonds. Deuterium was implanted at energies of 15, 25 and 35 keV and at a dose of 1x1014/cm2. Some of the wafers were subjected to N2O annealing following gate oxide growth. It was demonstrated that ion implantation is an effective means of introduction of deuterium. Deuterium implantation brings about a clear enhancement in gate oxide quality by improving the interface characteristics. N2O annealing further improves device performance. A reduction of electron traps with deutenum was also observed. A combination of deuterium implantation at 25 keV and a dose of 1x1015/cm2, followed by annealing in N2O was observed to have the most positive influence on device behavior.
Concurrently, MEMS microheaters being fabricated for an integrated VOC sensor were also tested for their temperature response to an applied voltage. Different channel configurations and materials for the conducting film were compared and the best pattern for rapid heating was identified. Temperature rises of upto 390° C were obtained. The temperature responses after coating spin-on glass in the microchannels were also measured
Radiation Effects in CMOS Isolation Oxides: Differences and Similarities With Thermal Oxides
Radiation effects in thick isolation oxides of modern CMOS technologies are investigated using dedicated test structures designed using two commercial foundries. Shallow Trench Isolation and Pre-Metal Dielectric are studied using electrical measurements performed after X-ray irradiations and isochronal annealing cycles. This paper shows that trapping properties of such isolation oxides can strongly differ from those of traditional thermal oxides usually used to process the gate oxide of Metal Oxide Semiconductor Field Effect Transistors. Buildup and annealing of both radiation-induced oxide-trap charge and radiation-induced interface traps are discussed as a function of the oxide type, foundry and bias condition during irradiation. Radiation-induced interface traps in such isolation oxides are shown to anneal below 100°C contrary to what is usually observed in thermal oxides. Implications for design hardening and radiation tests of CMOS Integrated Circuits are discussed
Nanocluster-rich SiO2 layers produced by ion beam synthesis: electrical and optoelectronic properties
The aim of this work was to find a correlation between the electrical, optical and microstructural properties of thin SiO2 layers containing group IV nanostructures produced by ion beam synthesis. The investigations were focused on two main topics: The electrical properties of Ge- and Si-rich oxide layers were studied in order to check their suitability for non-volatile memory applications. Secondly, photo- and electroluminescence (PL and EL) results of Ge-, Si/C- and Sn-rich SiO2 layers were compared to electrical properties to get a better understanding of the luminescence mechanism
Physics and Technology of Silicon Carbide Devices
Recently, some SiC power devices such as Schottky-barrier diodes (SBDs), metal-oxide-semiconductor field-effect-transistors (MOSFETs), junction FETs (JFETs), and their integrated modules have come onto the market. However, to stably supply them and reduce their cost, further improvements for material characterizations and those for device processing are still necessary. This book abundantly describes recent technologies on manufacturing, processing, characterization, modeling, and so on for SiC devices. In particular, for explanation of technologies, I was always careful to argue physics underlying the technologies as much as possible. If this book could be a little helpful to progress of SiC devices, it will be my unexpected happiness
Ultra-thin plasma nitrided oxide gate dielectrics for advanced MOS transistors
Ultra-thin plasma nitrided oxides have been optimized with the objective to decrease JG and maximize carrier mobility. It was found that while the base oxide cannot be aggressively scaled, plasma optimization yields better mobility thereby increase transistor performance. A summary of the EOT versus gate leakage current density of NMOS devices with plasma nitrided oxides is shown in Figure 5.19. EOT down to 1.2 nm has been achieved with a gate leakage current density of 40 A/cm2 at 1 V operating voltage
Preparation and properties of high dose nitrogen implanted epitaxially grown gadolinium oxide on silicon
[no abstract
Characterisation of silicon carbide CMOS devices for high temperature applications
PhD ThesisIn recent years it has become increasingly apparent that there is a large demand for resilient electronics that
can operate within environments that standard silicon electronics cease to function such as high power and high
voltage applications, high temperatures, corrosive atmospheres and environments exposed to radiation. This
has become even more essential due to increased demands for sustainable energy production and the reduction
in carbon emissions worldwide, which has put a large burden on a wide range of industrial sectors who now
have a significant demand for electronics to meet these needs including; military, space, aerospace, automotive,
energy and nuclear. In extreme environments, where ambient temperatures may well exceed the physical limit
of silicon-based technologies, SiC based technology offers a lower cost and a smaller footprint solution for
operation in such environments due to its advantageous electrical properties such as a high breakdown electric
field, high thermal conductivity and large saturation velocity. High quality material on large area wafers (150
mm) is now commercially available, allowing the fabrication of reliable high temperature, high frequency and
high current power electronic devices, improving the already optimised silicon based structures. An important
advantage of SiC is that it is the only wide band gap compound semiconductor that can be thermally oxidised
to grow insulating, high quality SiO2 layers, which makes it an ideal candidate to replace silicon technologies
for metal-oxide-semiconductor applications, which is the main focus of this research. Although the technology
has made a number of major steps forward over recent years and the commercial manufacturing process has
advanced significantly, there still remains a number of issues that need to be overcome in order to fully realise
the potential of the material for electronic applications.
This thesis describes the characterisation of 4H-SiC CMOS structures that were designed for high temperature
applications and fabricated with varying gate dielectric treatments and process steps. The influence of
process techniques on the characteristics of metal-oxide-semiconductor (MOS) devices has been investigated
by means of electrical characterisation and the results have been compared to theoretical models. The C-V and
I-V characteristics of both MOS capacitor and MOSFET structures with varying gate dielectrics on both n-type
and p-type 4H-SiC have been analysed to explore the benefits of the varying process techniques that have been
employed in the design of the devices.
The results show that the field effect mobility characteristic of 4H-SiC MOSFETs are dominated at low
perpendicular electric fields by Coulomb scattering and at high electric fields by low surface roughness mobility,
which is due to the rough SiC-SiO2 interface. The findings also show that a thermally grown SiO2 layer at the
semiconductor-dielectric interface is a beneficial process step that enhances the interfacial characteristics and
increases the channel mobility of the MOSFETs. In addition to this it is also found that this technique provides
the most beneficial characteristics on both n-type and p-type 4H-SiC, which suggests that it would be the most
suitable treatment for a monolithic CMOS process.
The impact of threshold voltage adjust ion implantation on both the MIS capacitor and MOSFET structures
is also presented and shows that the increasing doses of nitrogen that are implanted to adjust the threshold
voltage act to improve the device performance by acting to modify the charge at the interface or within the gate
oxide and therefore increase the field effect mobility of the studied devices.Engineering and Physical Sciences Research Council (EPSRC) and Raytheon
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