Product assurance technology for custom LSI/VLSI electronics

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification

Implementation and Characterisation of Monolithic CMOS Pixel Sensors for the CLIC Vertex and Tracking Detectors

Different CMOS technologies are being considered for the vertex and tracking layers of the detector at the proposed high-energy e$^{+}$e$^{−}$ Compact Linear Collider (CLIC). CMOS processes have been proven to be suitable for building high granularity, large area detector systems with low material budget and low power consumption. An effort is put on implementing detectors capable of performing precise timing measurements. Two Application-Specific Integrated Circuits (ASICs) for particle detection have been developed in the framework of this thesis, following the specifications of the CLIC vertex and tracking detectors. The process choice was based on a study of the features of each of the different available technologies and an evaluation of their suitability for each application. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is a pixelated detector chip designed to be used in capacitively coupled assemblies with the CLICpix2 readout chip, in the framework of the vertex detector at CLIC. The chip comprises a matrix of 128×128 square pixels with 25 µm pitch. A commercial 180 nm High-Voltage (HV) CMOS process was used for the C3PD design. The charge is collected with a large deep N-well, while each pixel includes a preamplifier placed on top of the collecting electrode. The C3PD chip was produced on wafers with different values for the substrate resistivity (∼ 20, 80, 200 and 1000 Ωcm) and has been extensively tested through laboratory measurements and beam tests. The design details and characterisation results of the C3PD chip will be presented. The CLIC Tracker Detector (CLICTD) is a novel monolithic detector chip developed in the context of the silicon tracker at CLIC. The CLICTD chip combines high density, mixed mode circuits on the same substrate, while it performs a fast time-tagging measurement with 10 ns time bins. The chip is produced in a 180 nm CMOS imaging process with a High-Resistivity (HR) epitaxial layer. A matrix of 16×128 detecting cells, each measuring 300 × 30 µm$^{2}$ , is included. A small N-well is used to collect the charge generated in the sensor volume, while an additional deep N-type implant is used to fully deplete the epitaxial layer. Using a process split, additional wafers are produced with a segmented deep N-type implant, a modification that has been simulated to result in a faster charge collection time. Each detecting cell is segmented into eight front-ends to ensure prompt charge collection in the sensor diodes. A simultaneous 8-bit timing and 5-bit energy measurement is performed in each detecting cell. A detailed description of the CLICTD design will be given, followed by the first measurement results

Digital control for automating feed distribution in feedlots

An investigation was conducted to determine the feasibility of automatic controls to automate feed distribution in feedlots. The control approach was restricted to compatibility with conventional feeding equipment. Input control signals were taken to originate from commonly available mechanical and electronic sensors. The control system was implemented with standard digital logic components;The proposed digital control system is based on a railguided, self-propelled automatic vehicle capable of delivering feed sequentially to 255 pens located on both sides of a single feeding path. A manual, closed-loop control system consisting of the following functions was developed: (1) pen identification, (2) initialization control, (3) feeding mode, (4) exit from feeding mode, (5) re-entry into feeding mode, (6) end of feeding cycle, (7) ground drive and conveyor control, (8) interface and auto/manual mode, (9) monitoring of automated system and (10) data and failure display and alarm. The control system allows either automatic or manual operation of the feeding vehicle. Digital electronic circuits capable of implementing the desired control functions were designed;The feeding cycle is manually initiated and automatically terminated when feed has been delivered to all pens requiring feed. It can be partially programmed to enable feed delivery to sections of the feedlot. Two feed rations can be delivered. The feeding status of each pen is recorded. The pen feed rations are stored in reprogrammable memories;The operation of the automated feeding system is based on the automatic identification of the feedlot pens. The number assigned to a pen is coded, using binary pulse-code modulation. Frequency-shift keying is used to transmit the coded number. The received coded number is recovered by specialized communication circuits and then validated;The control system monitors the vehicle components and the major electronic circuits to detect failures, prevent damage and produce a safe operation. Furthermore, it incorporates safety sensors and logic circuitry to meet the basic safety requirements pertaining to automated vehicles;The proposed automated feed distribution system for feedlots is expected to: (1) reduce management requirements through automatic distribution of feed to cattle raised in pens, (2) increase efficiency of feeding operation by eliminating time losses associated with secondary feed transfer, (3) eliminate damage to feedbunks through positive guidance of the vehicle by rails, and (4) save energy by eliminating secondary feed transfer

Rapid mapping of digital integrated circuit logic gates via multi-spectral backside imaging

Modern semiconductor integrated circuits are increasingly fabricated at untrusted third party foundries. There now exist myriad security threats of malicious tampering at the hardware level and hence a clear and pressing need for new tools that enable rapid, robust and low-cost validation of circuit layouts. Optical backside imaging offers an attractive platform, but its limited resolution and throughput cannot cope with the nanoscale sizes of modern circuitry and the need to image over a large area. We propose and demonstrate a multi-spectral imaging approach to overcome these obstacles by identifying key circuit elements on the basis of their spectral response. This obviates the need to directly image the nanoscale components that define them, thereby relaxing resolution and spatial sampling requirements by 1 and 2 - 4 orders of magnitude respectively. Our results directly address critical security needs in the integrated circuit supply chain and highlight the potential of spectroscopic techniques to address fundamental resolution obstacles caused by the need to image ever shrinking feature sizes in semiconductor integrated circuits

Single-Photon Avalanche Diodes in CMOS Technologies for Optical Communications

As optical communications may soon supplement Wi-Fi technologies, a concept known as visible light communications (VLC), low-cost receivers must provide extreme sensitivity to alleviate attenuation factors and overall power usage within communications link budgets. We present circuits with an advantage over conventional optical receivers, in that gain can be applied within the photodiode thus reducing the need for amplification circuits. To achieve this, single-photon avalanche diodes (SPADs) can be implemented in complementary metal-oxide-semiconductor (CMOS) technologies and have already been investigated in several topologies for VLC. The digital nature of SPADs removes the design effort used for low-noise, high-gain but high-bandwidth analogue circuits. We therefore present one of these circuit topologies, along with some common design and performance metrics. SPAD receivers are however not yet mature prompting research to take low-level parameters up to the communications level

Engineering study for a mass memory system for advanced spacecrafts Final report, 1 Dec. 1969 - 1 Jul. 1970

Mass memory system for advanced spacecraf

High-Speed Wide-Field Time-Correlated Single-Photon Counting Fluorescence Lifetime Imaging Microscopy

Fluorescence microscopy is a powerful imaging technique used in the biological sciences to identify labeled components of a sample with specificity. This is usually accomplished through labeling with fluorescent dyes, isolating these dyes by their spectral signatures with optical filters, and recording the intensity of the fluorescent response. Although these techniques are widely used, fluorescence intensity images can be negatively affected by a variety of factors that impact the fluorescence intensity. Fluorescence lifetime imaging microscopy (FLIM) is an imaging technique that is relatively immune to intensity fluctuations and also provides the unique ability to directly monitor the microenvironment surrounding a fluorophore. Despite the benefits associated with FLIM, the applications to which it is applied are fairly limited due to long image acquisition times and high cost of traditional hardware. Recent advances in complementary metal-oxide-semiconductor (CMOS) single-photon avalanche diodes (SPADs) have enabled the design of low-cost imaging arrays that are capable of recording lifetime images with acquisition times greater than one order of magnitude faster than existing systems. However, these SPAD arrays have yet to realize the full potential of the technology due to limitations in their ability to handle the vast amount of data generated during the commonly used time-correlated single-photon counting (TCSPC) lifetime imaging technique. This thesis presents the design, implementation, characterization, and demonstration of a high speed FLIM imaging system. The components of this design include a CMOS imager chip in a standard 0.13 μm technology containing a custom CMOS SPAD, a 64-by-64 array of these SPADs, pixel control circuitry, independent time-to-digital converters (TDCs), a FLIM specific datapath, and high bandwidth output buffers. In addition to the CMOS imaging array, a complete system was designed and implemented using a printed circuit board (PCB) for capturing data from the imager, creating histograms for the photon arrival data using field-programmable gate arrays, and transferring the data to a computer using a cabled PCIe interface. Finally, software is used to communicate between the imaging system and a computer.The dark count rate of the SPAD was measured to be only 231 Hz at room temperature while maintaining a photon detection probability of up to 30\%. TDCs included on the array have a 62.5 ps resolution and a 64 ns range, which is suitable for measuring the lifetime of most biological fluorophores. Additionally, the on-chip datapath was designed to handle continuous data transfers at rates capable of supporting TCSPC-based lifetime imaging at 100 frames per second. The system level implementation also provides sufficient data throughput for transferring up to 750 frames per second from the imaging system to a computer. The lifetime imaging system was characterized using standard techniques for evaluating SPAD performance and an electrical delay signal for measuring the TDC performance. This thesis concludes with a demonstration of TCSPC-FLIM imaging at 100 frames per second -- the fastest 64-by-64 TCSPC FLIM that has been demonstrated. This system overcomes some of the limitations of existing FLIM systems and has the potential to enable new application domains in dynamic FLIM imaging

EMI Susceptibility Issue in Analog Front-End for Sensor Applications

The susceptibility to electromagnetic interferences of the analog circuits used in the sensor readout front-end is discussed. Analog circuits still play indeed a crucial role in sensor signal acquisition due to the analog nature of sensory signals. The effect of electromagnetic interferences has been simulated and measured in many commercial and integrated analog circuits; the main cause of the electromagnetic susceptibility is investigated and the guidelines to design high EMI immunity circuits are provided

A self-powered single-chip wireless sensor platform

Internet of things” require a large array of low-cost sensor nodes, wireless connectivity, low power operation and system intelligence. On the other hand, wireless biomedical implants demand additional specifications including small form factor, a choice of wireless operating frequencies within the window for minimum tissue loss and bio-compatibility This thesis describes a low power and low-cost internet of things system suitable for implant applications that is implemented in its entirety on a single standard CMOS chip with an area smaller than 0.5 mm2. The chip includes integrated sensors, ultra-low-power transceivers, and additional interface and digital control electronics while it does not require a battery or complex packaging schemes. It is powered through electromagnetic (EM) radiation using its on-chip miniature antenna that also assists with transmit and receive functions. The chip can operate at a short distance (a few centimeters) from an EM source that also serves as its wireless link. Design methodology, system simulation and optimization and early measurement results are presented