Aceleradores e multiprocessadores em chip: o impacto da execução fora de ordem na verificação de funcionalidade e de consistência

Dissertação (mestrado) - Universidade Federal de Santa Catarina, Centro Tecnológico, Programa de Pós-Graduação em Ciência da Computação, Florianópolis, 2012Este trabalho aborda duas classes de problemas enfrentados na verificação de projetos que exibem comportamentos fora de ordem, especificamente a verificação funcional de aceleradores em hardware e a verificação de consistência em sistemas de memória compartilhada. Comportamentos fora de ordem surgem quando relaxam-se restrições de precedência para aumentar a taxa de uso de componentes de hardware concorrentes e, portanto, aumentar o desempenho. Entretanto, o projeto de um sistema que apresenta comportamentos fora de ordem é suscetível a erros pelo fato de o relaxamento de ordem requerer controle sofisticado. Este trabalho compara as garantias de verificação de três classes de checkers dinâmicos para módulos com suporte a eventos fora de ordem. Comprovadamente, scoreboards relaxados podem ser construídos com plenas garantias de verificação contanto que utilizem regras de atualização baseadas na remoção de dominadores. Resultados experimentais mostram que um scoreboard relaxado assim projetado requer aproximadamente 1/2 do esforço exigido por um scoreboard convencional. Verificar a conformidade do hardware com um modelo de consistência é um problema relevante cuja complexidade depende da observabilidade dos eventos de memória. Este trabalho também descreve uma nova técnica de verificação de consistência de memória on-the-fly a partir de uma representação executável de um sistema multi-core. Para aumentar a eficiência sem afetar as garantias de verificação, são monitorados três pontos por núcleo, ao invés de um ou dois, como proposto em trabalhos correlatos anteriores. Os três pontos foram selecionados para serem altamente independentes da microarquitetura do core. A técnica usa scoreboards relaxados concorrentes para detectar violações em cada core. Para detectar violações globais, utiliza-se a ordem linear de eventos induzida por um caso de teste. Comprovadamente, a técnica não induz falsos positivos nem falsos negativos quando o caso de teste expõe um erro que afeta as sequências monitoradas, tornando-se o primeiro checker on-the-fly com plenas garantias de verificação. Resultados experimentais mostram que ele requer aproximadamente 1/4 a 3/4 do esforço global exigido por um checker post-mortem que monitora duas sequências por processador. A técnica é pelo menos 100 vezes mais rápida do que um checker que monitora uma única sequência por processador.Abstract : This work addresses two classes of problems faced when verifying designs exhibiting out-of-order behaviors, namely the functional verification of hardware accelerators and the verification of consistency in shared-memory systems. Out-of-order behaviors result from relaxing precedence constraints to increase the usage rate of concurrent hardware components and, therefore, lead to a performance improvement. However, the design of a system handling out-of-order behaviors is error prone, since order relaxation asks for sophisticated control. This work compares the verification guarantees of three classes of dynamic checkers for modules handling out-of-order behaviors. Provenly, relaxed scoreboards can be built with full verification guarantees, as far as they employ an update rule based on the removal of dominators. Experimental results show that such a relaxed scoreboard needs approximately 1/2 of the effort required by a conventional one. Verifying the hardware compliance with a consistency model is a relevant problem, whose complexity depends on the observability of memory events. This work also describes a novel on-the-fly technique for verifying memory consistency from an executable representation of a multi-core system. To increase efficiency without hampering verification guarantees, three points are monitored per core, instead of one or two, as proposed in previous related works. The points were selected to be largely independent from the core#s microarchitecture. The technique relies on concurrent relaxed scoreboards to check for consistency violations in each core. To check for global violations, it employs a linear order of events induced by a given test case. Provenly, the technique neither indicates false negatives nor false positives when the test case exposes an error that affects the sampled sequences, making it the first on-the-fly checker with full guarantees. Experimental results show that it needs approximately 1/4 to 3/4 of the overall verification effort required by a post-mortem checker sampling two sequences per processor. The technique is at least 100 times faster than a checker sampling a single sequence per processor

Memory consistency directed cache coherence protocols for scalable multiprocessors

The memory consistency model, which formally specifies the behavior of the memory system, is used by programmers to reason about parallel programs. From a hardware design perspective, weaker consistency models permit various optimizations in a multiprocessor system: this thesis focuses on designing and optimizing the cache coherence protocol for a given target memory consistency model. Traditional directory coherence protocols are designed to be compatible with the strictest memory consistency model, sequential consistency (SC). When they are used for chip multiprocessors (CMPs) that provide more relaxed memory consistency models, such protocols turn out to be unnecessarily strict. Usually, this comes at the cost of scalability, in terms of per-core storage due to sharer tracking, which poses a problem with increasing number of cores in today’s CMPs, most of which no longer are sequentially consistent. The recent convergence towards programming language based relaxed memory consistency models has sparked renewed interest in lazy cache coherence protocols. These protocols exploit synchronization information by enforcing coherence only at synchronization boundaries via self-invalidation. As a result, such protocols do not require sharer tracking which benefits scalability. On the downside, such protocols are only readily applicable to a restricted set of consistency models, such as Release Consistency (RC), which expose synchronization information explicitly. In particular, existing architectures with stricter consistency models (such as x86) cannot readily make use of lazy coherence protocols without either: adapting the protocol to satisfy the stricter consistency model; or changing the architecture’s consistency model to (a variant of) RC, typically at the expense of backward compatibility. The first part of this thesis explores both these options, with a focus on a practical approach satisfying backward compatibility. Because of the wide adoption of Total Store Order (TSO) and its variants in x86 and SPARC processors, and existing parallel programs written for these architectures, we first propose TSO-CC, a lazy cache coherence protocol for the TSO memory consistency model. TSO-CC does not track sharers and instead relies on self-invalidation and detection of potential acquires (in the absence of explicit synchronization) using per cache line timestamps to efficiently and lazily satisfy the TSO memory consistency model. Our results show that TSO-CC achieves, on average, performance comparable to a MESI directory protocol, while TSO-CC’s storage overhead per cache line scales logarithmically with increasing core count. Next, we propose an approach for the x86-64 architecture, which is a compromise between retaining the original consistency model and using a more storage efficient lazy coherence protocol. First, we propose a mechanism to convey synchronization information via a simple ISA extension, while retaining backward compatibility with legacy codes and older microarchitectures. Second, we propose RC3 (based on TSOCC), a scalable cache coherence protocol for RCtso, the resulting memory consistency model. RC3 does not track sharers and relies on self-invalidation on acquires. To satisfy RCtso efficiently, the protocol reduces self-invalidations transitively using per-L1 timestamps only. RC3 outperforms a conventional lazy RC protocol by 12%, achieving performance comparable to a MESI directory protocol for RC optimized programs. RC3’s storage overhead per cache line scales logarithmically with increasing core count and reduces on-chip coherence storage overheads by 45% compared to TSO-CC. Finally, it is imperative that hardware adheres to the promised memory consistency model. Indeed, consistency directed coherence protocols cannot use conventional coherence definitions (e.g. SWMR) to be verified against, and few existing verification methodologies apply. Furthermore, as the full consistency model is used as a specification, their interaction with other components (e.g. pipeline) of a system must not be neglected in the verification process. Therefore, verifying a system with such protocols in the context of interacting components is even more important than before. One common way to do this is via executing tests, where specific threads of instruction sequences are generated and their executions are checked for adherence to the consistency model. It would be extremely beneficial to execute such tests under simulation, i.e. when the functional design implementation of the hardware is being prototyped. Most prior verification methodologies, however, target post-silicon environments, which when used for simulation-based memory consistency verification would be too slow. We propose McVerSi, a test generation framework for fast memory consistency verification of a full-system design implementation under simulation. Our primary contribution is a Genetic Programming (GP) based approach to memory consistency test generation, which relies on a novel crossover function that prioritizes memory operations contributing to non-determinism, thereby increasing the probability of uncovering memory consistency bugs. To guide tests towards exercising as much logic as possible, the simulator’s reported coverage is used as the fitness function. Furthermore, we increase test throughput by making the test workload simulation-aware. We evaluate our proposed framework using the Gem5 cycle accurate simulator in full-system mode with Ruby (with configurations that use Gem5’s MESI protocol, and our proposed TSO-CC together with an out-of-order pipeline). We discover 2 new bugs in the MESI protocol due to the faulty interaction of the pipeline and the cache coherence protocol, highlighting that even conventional protocols should be verified rigorously in the context of a full-system. Crucially, these bugs would not have been discovered through individual verification of the pipeline or the coherence protocol. We study 11 bugs in total. Our GP-based test generation approach finds all bugs consistently, therefore providing much higher guarantees compared to alternative approaches (pseudo-random test generation and litmus tests)

What Happens Now? Coaching and Leading Following a Student-Athlete Death - A Phenomenological Study

College students die and sometimes these students are student-athletes. This transcendental phenomenological study described and explored the lived leadership experiences, related to the components of Transformational Leadership, of NCAA sports team coaches who led their team following an unexpected death of a student-athlete. No research to date had focused on this leadership phenomenon. Five NCAA sport team head coaches participated in semi-structured interviews to learn more about their coaching leadership experiences during this time of crisis. The study participants shared their intensely emotional and personal leadership experiences of leading and coaching their teams during a time of crisis. There were four main emergent themes with several sub-themes. These were Emotion, Leadership Challenges, Growth as a Leader and University Response and Reaction. Several sub-themes were found to support Bass and Riggio\u27s (2006) four components of the Transformational Leadership theory of Idealized Influence, Individual Consideration, Inspirational Motivation and Intellectual Stimulation. Beyond emergent themes, utilizing Coliazzi\u27s method (1978) of phenomenological analysis, the essence of experience of this coaching leadership phenomenon was created. This study confirmed Bass and Riggio\u27s (2006) components of Transformational Leadership theory as a valid framework to examine both crisis leadership and coaching leadership behaviors in sports. This study increased understanding of the phenomenon of sport team coaches leading their teams following the unexpected death of a student-athlete, while providing insights and strategies for coaches and athlete administrators to utilize in the future

Town of Hanover, 2008 Annual town report.

This is an annual report containing vital statistics for a town/city in the state of New Hampshire

Harnessing Simulation Acceleration to Solve the Digital Design Verification Challenge.

Today, design verification is by far the most resource and time-consuming activity of any new digital integrated circuit development. Within this area, the vast majority of the verification effort in industry relies on simulation platforms, which are implemented either in hardware or software. A "simulator" includes a model of each component of a design and has the capability of simulating its behavior under any input scenario provided by an engineer. Thus, simulators are deployed to evaluate the behavior of a design under as many input scenarios as possible and to identify and debug all incorrect functionality. Two features are critical in simulators for the validation effort to be effective: performance and checking/debugging capabilities. A wide range of simulator platforms are available today: on one end of the spectrum there are software-based simulators, providing a very rich software infrastructure for checking and debugging the design's functionality, but executing only at 1-10 simulation cycles per second (while actual chips operate at GHz speeds). At the other end of the spectrum, there are hardware-based platforms, such as accelerators, emulators and even prototype silicon chips, providing higher performances by 4 to 9 orders of magnitude, at the cost of very limited or non-existent checking/debugging capabilities. As a result, today, simulation-based validation is crippled: one can either have satisfactory performance on hardware-accelerated platforms or critical infrastructures for checking/debugging on software simulators, but not both. This dissertation brings together these two ends of the spectrum by presenting solutions that offer high-performance simulation with effective checking and debugging capabilities. Specifically, it addresses the performance challenge of software simulators by leveraging inexpensive off-the-shelf graphics processors as massively parallel execution substrates, and then exposing the parallelism inherent in the design model to that architecture. For hardware-based platforms, the dissertation provides solutions that offer enhanced checking and debugging capabilities by abstracting the relevant data to be logged during simulation so to minimize the cost of collection, transfer and processing. Altogether, the contribution of this dissertation has the potential to solve the challenge of digital design verification by enabling effective high-performance simulation-based validation.PHDComputer Science and EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/99781/1/dchatt_1.pd

Proceedings, MSVSCC 2012

Proceedings of the 6th Annual Modeling, Simulation & Visualization Student Capstone Conference held on April 19, 2012 at VMASC in Suffolk, Virginia

An aesthetic for sustainable interactions in product-service systems?

Copyright @ 2012 Greenleaf PublishingEco-efficient Product-Service System (PSS) innovations represent a promising approach to sustainability. However the application of this concept is still very limited because its implementation and diffusion is hindered by several barriers (cultural, corporate and regulative ones). The paper investigates the barriers that affect the attractiveness and acceptation of eco-efficient PSS alternatives, and opens the debate on the aesthetic of eco-efficient PSS, and the way in which aesthetic could enhance some specific inner qualities of this kinds of innovations. Integrating insights from semiotics, the paper outlines some first research hypothesis on how the aesthetic elements of an eco-efficient PSS could facilitate user attraction, acceptation and satisfaction

The Whitworthian 2004-2005

The Whitworthian student newspaper, September 2004-May 2005.https://digitalcommons.whitworth.edu/whitworthian/1088/thumbnail.jp

Gamification as a tool for developing critical thinking among ICT students at a tertiary institution in South Africa

Thesis (MTech (Business Information Systems))--Cape Peninsula University of Technology, 2019The recent generation of students, often referred to as ‘Millennials’, are generally familiar with computer games and therefore learn mostly through virtual experiences from game playing. A high failure rate due to the lack of critical thinking (CT) skills among tertiary students still persists, despite the implementation of CT enhancing programmes and frameworks. The aim of this research was to explore the effect of gamification on the critical thinking skills of Information and Communications Technology (ICT) students. A single pre-and post-quasi-experimental research strategy with a pragmatic perspective research approach was followed. Mixed methods research with self-administered semi-structured questionnaires and interviews was employed. In total, 182 questionnaires distributed to students were analysed pre- and post-intervention, and five (5) interviews were conducted with the relevant lecturers post-intervention. The data were summarised and categorised by applying thematic analysis. All participants volunteered to be part of the study, and they were informed of the confidentiality and anonymity of the research before partaking in the study. From the inductive study results, it was found that CT is already an integral part of the subject content being taught to the students. The experimental learning environment did not result in significant domain-general CT compared to the control environment. Judgement was the only CT skills element showing a significant improvement from pre- to post-results on the respondents’ overall CT. Gamification can be an effectual instrument to enhance CT skills, as it enables the retention of knowledge through play by motivating and stimulating inquisitiveness among students

Inter-Municipal Cooperation as a Tool of Resilience in Small Communities

The hypothesis of the paper is that the resilience of small communities can be engaged by inter-municipal cooperation. The economy of scale of public services is a great challenge for the small communities in Europe. The review of the international models will focus on the models based on the merge of the municipalities and on the models based on the engagement of inter-municipal cooperation. The literature on these reforms will be reviewed. Based on the hypothesis, the regulation on inter-municipal cooperation and service provision of the rural areas in Hungary in the last two decades will be shortly presented. As part of this research, empirical research was carried out in a Hungarian rural area, which has a strong inter-municipal cooperation. Similarly, empirical research has been carried out in a Slovenian rural area which is based on the merge of the small communities. The advantages and disadvantages of the inter-municipal model, and the model based on the merge of the communities were compared in the paper: efficient units of public services provision can be established not only by the merge of the communities but by the establishment of inter-municipal associations. Although decision-making is more complicated, the small communities could be more resilient based on this model, because the flexibility and the community building of the small municipal model prevail as well. The merge of the municipalities offers more efficient decision-making, but the resilience engaged by the grassroots service provision requires some administrative actions in this model