Electromigration modeling and layout optimization for advanced VLSI

textElectromigration (EM) is a critical problem for interconnect reliability in advanced VLSI design. Because EM is a strong function of current density, a smaller cross-sectional area of interconnects can degrade the EM-related lifetime of IC, which is expected to become more severe in future technology nodes. Moreover, as EM is governed by various factors such as temperature, material property, geometrical shape, and mechanical stress, different interconnect structures can have distinct EM issues and solutions to mitigate them. For example, one of the most prominent technologies, die stacking technology of three-dimensional (3D) ICs, can have different EM problems from that of planer ICs, due to their unique interconnects such as through-silicon vias (TSVs). This dissertation investigates EM in various interconnect structures, and applies the EM models to optimize IC layout. First, modeling of EM is developed for chip-level interconnects, such as wires, local vias, TSVs, and multi-scale vias (MSVs). Based on the models, fast and accurate EM-prediction methods are proposed for the chip-level designs. After that, by utilizing the EM-prediction methods, the layout optimization methods are suggested, such as EM-aware routing for 3D ICs and EM-aware redundant via insertion for the future technology nodes in VLSI. Experimental results show that the proposed EM modeling approaches enable fast and accurate EM evaluation for chip design, and the EM-aware layout optimization methods improve EM-robustness of advanced VLSI designs.Electrical and Computer Engineerin

Macro-model of through silicon vias (tsvs) arrays

As continued scaling down of transistors becomes increasingly difficult due to physical and technical issues like the increase of leakage power and total power consumption, overall, 3D integration is now considered a viable solution to get a higher bandwidth and power efficiency. Use of Through-silicon-vias (TSVs), which connects stacked structures die-to-die, is expected to be one of the most important techniques enabling 3D integration. As the number of through silicon Vias (TSVs) exists in the same chip is increasing, an algorithm to build a macro-model is needed to find inter-relationship between TSVs. There are different coupling parameters that exist between TSVs like: capacitive, inductive and resistive coupling. This work provides an algorithm to build a macro-model of an array of TSVs where only capacitive coupling is considered, as it is expected to be the dominating parameter.Using a simulation based technique, where characterization for bundles of TSVs were done and a scaling equation that can give the variationsoccur to capacitance value with scaling the physical dimensions of the TSV (pitch, radius, length and dielectric thickness (tox)) is proposed. The considered ranges for the physical parameters are: radius (from 1um to 10um), tox (from 0.1um to 0.5 um), length (from 10um to 100um) and pitch (from 10um to 95um). Using theproposed algorithm, a macro model can be built in a negligible time, which provides lots of time saving compared to hours required by other tools such as EM simulators or device simulators. The average error range 3% to 6%and a maximum cumulative error of algorithm and usage of scaling equation is 18.2% that occurs at very few dimensions and in very few capacitances from the extracted capacitance values, for both self and coupling capacitance

Enabling Technologies for 3D ICs: TSV Modeling and Analysis

Through silicon via (TSV) based three-dimensional (3D) integrated circuit (IC) aims to stack and interconnect dies or wafers vertically. This emerging technology offers a promising near-term solution for further miniaturization and the performance improvement of electronic systems and follows a more than Moore strategy. Along with the need for low-cost and high-yield process technology, the successful application of TSV technology requires further optimization of the TSV electrical modeling and design. In the millimeter wave (mmW) frequency range, the root mean square (rms) height of the TSV sidewall roughness is comparable to the skin depth and hence becomes a critical factor for TSV modeling and analysis. The impact of TSV sidewall roughness on electrical performance, such as the loss and impedance alteration in the mmW frequency range, is examined and analyzed following the second order small perturbation method. Then, an accurate and efficient electrical model for TSVs has been proposed considering the TSV sidewall roughness effect, the skin effect, and the metal oxide semiconductor (MOS) effect. However, the emerging application of 3D integration involves an advanced bio-inspired computing system which is currently experiencing an explosion of interest. In neuromorphic computing, the high density membrane capacitor plays a key role in the synaptic signaling process, especially in a spike firing analog implementation of neurons. We proposed a novel 3D neuromorphic design architecture in which the redundant and dummy TSVs are reconfigured as membrane capacitors. This modification has been achieved by taking advantage of the metal insulator semiconductor (MIS) structure along the sidewall, strategically engineering the fixed oxide charges in depletion region surrounding the TSVs, and the addition of oxide layer around the bump without changing any process technology. Without increasing the circuit area, these reconfiguration of TSVs can result in substantial power consumption reduction and a significant boost to chip performance and efficiency. Also, depending on the availability of the TSVs, we proposed a novel CAD framework for TSV assignments based on the force-directed optimization and linear perturbation

Physical Design Methodologies for Low Power and Reliable 3D ICs

As the semiconductor industry struggles to maintain its momentum down the path following the Moore's Law, three dimensional integrated circuit (3D IC) technology has emerged as a promising solution to achieve higher integration density, better performance, and lower power consumption. However, despite its significant improvement in electrical performance, 3D IC presents several serious physical design challenges. In this dissertation, we investigate physical design methodologies for 3D ICs with primary focus on two areas: low power 3D clock tree design, and reliability degradation modeling and management. Clock trees are essential parts for digital system which dissipate a large amount of power due to high capacitive loads. The majority of existing 3D clock tree designs focus on minimizing the total wire length, which produces sub-optimal results for power optimization. In this dissertation, we formulate a 3D clock tree design flow which directly optimizes for clock power. Besides, we also investigate the design methodology for clock gating a 3D clock tree, which uses shutdown gates to selectively turn off unnecessary clock activities. Different from the common assumption in 2D ICs that shutdown gates are cheap thus can be applied at every clock node, shutdown gates in 3D ICs introduce additional control TSVs, which compete with clock TSVs for placement resources. We explore the design methodologies to produce the optimal allocation and placement for clock and control TSVs so that the clock power is minimized. We show that the proposed synthesis flow saves significant clock power while accounting for available TSV placement area. Vertical integration also brings new reliability challenges including TSV's electromigration (EM) and several other reliability loss mechanisms caused by TSV-induced stress. These reliability loss models involve complex inter-dependencies between electrical and thermal conditions, which have not been investigated in the past. In this dissertation we set up an electrical/thermal/reliability co-simulation framework to capture the transient of reliability loss in 3D ICs. We further derive and validate an analytical reliability objective function that can be integrated into the 3D placement design flow. The reliability aware placement scheme enables co-design and co-optimization of both the electrical and reliability property, thus improves both the circuit's performance and its lifetime. Our electrical/reliability co-design scheme avoids unnecessary design cycles or application of ad-hoc fixes that lead to sub-optimal performance. Vertical integration also enables stacking DRAM on top of CPU, providing high bandwidth and short latency. However, non-uniform voltage fluctuation and local thermal hotspot in CPU layers are coupled into DRAM layers, causing a non-uniform bit-cell leakage (thereby bit flip) distribution. We propose a performance-power-resilience simulation framework to capture DRAM soft error in 3D multi-core CPU systems. In addition, a dynamic resilience management (DRM) scheme is investigated, which adaptively tunes CPU's operating points to adjust DRAM's voltage noise and thermal condition during runtime. The DRM uses dynamic frequency scaling to achieve a resilience borrow-in strategy, which effectively enhances DRAM's resilience without sacrificing performance. The proposed physical design methodologies should act as important building blocks for 3D ICs and push 3D ICs toward mainstream acceptance in the near future

Multiphysics modeling and simulation for large-scale integrated circuits

This dissertation is a process of seeking solutions to two important and challenging problems related to the design of modern integrated circuits (ICs): the ever increasing couplings among the multiphysics and the large problem size arising from the escalating complexity of the designs. A multiphysics-based computer-aided design methodology is proposed and realized to address multiple aspects of a design simultaneously, which include electromagnetics, heat transfer, fluid dynamics, and structure mechanics. The multiphysics simulation is based on the finite element method for its unmatched capabilities in handling complicate geometries and material properties. The capability of the multiphysics simulation is demonstrated through its applications in a variety of important problems, including the static and dynamic IR-drop analyses of power distribution networks, the thermal-ware high-frequency characterization of through-silicon-via structures, the full-wave electromagnetic analysis of high-power RF/microwave circuits, the modeling and analysis of three-dimensional ICs with integrated microchannel cooling, the characterization of micro- and nanoscale electrical-mechanical systems, and the modeling of decoupling capacitor derating in the power integrity simulations. To perform the large-scale analysis in a highly efficient manner, a domain decomposition scheme, parallel computing, and an adaptive time-stepping scheme are incorporated into the proposed multiphysics simulation. Significant reduction in computation time is achieved through the two numerical schemes and the parallel computing with multiple processors

High-Density Solid-State Memory Devices and Technologies

This Special Issue aims to examine high-density solid-state memory devices and technologies from various standpoints in an attempt to foster their continuous success in the future. Considering that broadening of the range of applications will likely offer different types of solid-state memories their chance in the spotlight, the Special Issue is not focused on a specific storage solution but rather embraces all the most relevant solid-state memory devices and technologies currently on stage. Even the subjects dealt with in this Special Issue are widespread, ranging from process and design issues/innovations to the experimental and theoretical analysis of the operation and from the performance and reliability of memory devices and arrays to the exploitation of solid-state memories to pursue new computing paradigms

Analyse et caractérisation des couplages substrat et de la connectique dans les circuits 3D : Vers des modèles compacts

The 3D integration is the most promising technological solution to track the level of integration dictated by Moore's Law (see more than Moore, Moore versus more). It leads to important research for a dozen years. It can superimpose different circuits and components in one box. Its main advantage is to allow a combination of heterogeneous and highly specialized technologies for the establishment of a complete system, while maintaining a high level of performance with very short connections between the different circuits. The objective of this work is to provide consistent modeling via crossing, and / or contacts in the substrate, with various degrees of finesse / precision to allow the high-level designer to manage and especially to optimize the partitioning between the different strata. This modelization involves the development of multiple views at different levels of abstraction: the physical model to "high level" model. This would allow to address various issues faced in the design process: - The physical model using an electromagnetic simulation based on 2D or 3D ( finite element solver ) is used to optimize the via (materials, dimensions etc..) It determines the electrical performance of the via, including high frequency. Electromagnetic simulations also quantify the coupling between adjacent via. - The analytical compact of via their coupling model, based on a description of transmission line or Green cores is used for the simulations at the block level and Spice type simulations. Analytical models are often validated against measurements and / or physical models.L’intégration 3D est la solution technologique la plus prometteuse pour suivre le niveau d’intégration dictée par la loi de Moore (cf. more than Moore, versus more Moore). Elle entraine des travaux de recherche importants depuis une douzaine d’années. Elle permet de superposer différents circuits et composants dans un seul boitier. Son principal avantage est de permettre une association de technologies hétérogènes et très spécialisées pour la constitution d’un système complet, tout en préservant un très haut niveau de performance grâce à des connexions très courtes entre ces différents circuits. L’objectif de ce travail est de fournir des modélisations cohérentes de via traversant, ou/et de contacts dans le substrat, avec plusieurs degrés de finesse/précision, pour permettre au concepteur de haut niveau de gérer et surtout d’optimiser le partitionnement entre les différentes strates. Cette modélisation passe par le développement de plusieurs vues à différents niveaux d’abstraction: du modèle physique au modèle « haut niveau ». Elle devait permettre de répondre à différentes questions rencontrées dans le processus de conception :- le modèle physique de via basé sur une simulation électromagnétique 2D ou 3D (solveur « éléments finis ») est utilisé pour optimiser l’architecture du via (matériaux, dimensions etc.) Il permet de déterminer les performances électriques des via, notamment en haute fréquence. Les simulations électromagnétiques permettent également de quantifier le couplage entre via adjacents. - le modèle compact analytique de via et de leur couplage, basé sur une description de type ligne de transmission ou noyaux de Green, est utilisé pour les simulations au niveau bloc, ainsi que des simulations de type Spice. Les modèles analytiques sont souvent validés par rapport à des mesures et/ou des modèles physiques

VLSI Design

This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc