Memory and information processing in neuromorphic systems

A striking difference between brain-inspired neuromorphic processors and current von Neumann processors architectures is the way in which memory and processing is organized. As Information and Communication Technologies continue to address the need for increased computational power through the increase of cores within a digital processor, neuromorphic engineers and scientists can complement this need by building processor architectures where memory is distributed with the processing. In this paper we present a survey of brain-inspired processor architectures that support models of cortical networks and deep neural networks. These architectures range from serial clocked implementations of multi-neuron systems to massively parallel asynchronous ones and from purely digital systems to mixed analog/digital systems which implement more biological-like models of neurons and synapses together with a suite of adaptation and learning mechanisms analogous to the ones found in biological nervous systems. We describe the advantages of the different approaches being pursued and present the challenges that need to be addressed for building artificial neural processing systems that can display the richness of behaviors seen in biological systems.Comment: Submitted to Proceedings of IEEE, review of recently proposed neuromorphic computing platforms and system

A Nanocryotron Ripple Counter Integrated with a Superconducting Nanowire Single-Photon Detector for Megapixel Arrays

Decreasing the number of cables that bring heat into the cryocooler is a critical issue for all cryoelectronic devices. Especially, arrays of superconducting nanowire single-photon detectors (SNSPDs) could require more than $10^6$ readout lines. Performing signal processing operations at low temperatures could be a solution. Nanocryotrons, superconducting nanowire three-terminal devices, are good candidates for integrating sensing and electronics on the same technological platform as SNSPDs in photon-counting applications. In this work, we demonstrated that it is possible to read out, process, encode, and store the output of SNSPDs using exclusively superconducting nanowires. In particular, we present the design and development of a nanocryotron ripple counter that detects input voltage spikes and converts the number of pulses to an $N$-digit value. The counting base can be tuned from 2 to higher values, enabling higher maximum counts without enlarging the circuit. As a proof-of-principle, we first experimentally demonstrated the building block of the counter, an integer-$N$ frequency divider with $N$ ranging from 2 to 5. Then, we demonstrated photon-counting operations at 405\,nm and 1550\,nm by coupling an SNSPD with a 2-digit nanocryotron counter partially integrated on-chip. The 2-digit counter operated in either base 2 or base 3 with a bit error rate lower than $2 \times 10^{-4}$ and a maximum count rate of $45 \times 10^6\,$s$^{-1}$. We simulated circuit architectures for integrated readout of the counter state, and we evaluated the capabilities of reading out an SNSPD megapixel array that would collect up to $10^{12}$ counts per second. The results of this work, combined with our recent publications on a nanocryotron shift register and logic gates, pave the way for the development of nanocryotron processors, from which multiple superconducting platforms may benefit

Optimum non linear binary image restoration through linear grey-scale operations

Non-linear image processing operators give excellent results in a number of image processing tasks such as restoration and object recognition. However they are frequently excluded from use in solutions because the system designer does not wish to introduce additional hardware or algorithms and because their design can appear to be ad hoc. In practice the median filter is often used though it is rarely optimal. This paper explains how various non-linear image processing operators may be implemented on a basic linear image processing system using only convolution and thresholding operations. The paper is aimed at image processing system developers wishing to include some non-linear processing operators without introducing additional system capabilities such as extra hardware components or software toolboxes. It may also be of benefit to the interested reader wishing to learn more about non-linear operators and alternative methods of design and implementation. The non-linear tools include various components of mathematical morphology, median and weighted median operators and various order statistic filters. As well as describing novel algorithms for implementation within a linear system the paper also explains how the optimum filter parameters may be estimated for a given image processing task. This novel approach is based on the weight monotonic property and is a direct rather than iterated method

Design of a fault tolerant airborne digital computer. Volume 1: Architecture

This volume is concerned with the architecture of a fault tolerant digital computer for an advanced commercial aircraft. All of the computations of the aircraft, including those presently carried out by analogue techniques, are to be carried out in this digital computer. Among the important qualities of the computer are the following: (1) The capacity is to be matched to the aircraft environment. (2) The reliability is to be selectively matched to the criticality and deadline requirements of each of the computations. (3) The system is to be readily expandable. contractible, and (4) The design is to appropriate to post 1975 technology. Three candidate architectures are discussed and assessed in terms of the above qualities. Of the three candidates, a newly conceived architecture, Software Implemented Fault Tolerance (SIFT), provides the best match to the above qualities. In addition SIFT is particularly simple and believable. The other candidates, Bus Checker System (BUCS), also newly conceived in this project, and the Hopkins multiprocessor are potentially more efficient than SIFT in the use of redundancy, but otherwise are not as attractive

Gallium arsenide design methodology and testing of a systolic floating point processing element

Thesis (M.E.Sc.) -- University of Adelaide, Dept. of Electrical and Electronic Engineering, 199

A computer-aided design for digital filter implementation

Imperial Users onl