Contributions to substrate noise due to supply coupling and pin parasitics

This thesis presents the contributions to substrate noise due to supply coupling and the effect of pin parasitics on the substrate noise generated by digital circuits. Various sources of substrate noise and their effect on analog circuits sharing the same substrate are discussed. A simulation approach to isolate the various components of substrate noise is elaborated. The importance of including package parasitic models in digital noise simulations is discussed and the dominance of supply inductance over the other package parasitic elements is established. The effects of transistor sizing and supply inductance on the noise picked up by a sensor placed close to a digital circuit are described. Some noise suppression techniques and their validation from measurements on a TSMC 0.35μm process mixed signal chip are also presented

Substrate coupling macromodel for lightly doped CMOS processes

A scalable macromodel for substrate noise coupling in lightly doped substrates with and without a buried layer has been developed. This model is based on Z-parameters and is scalable with contact size and separation. This model requires process dependent parameters that can be extracted easily from a small number of device simulations or measurements. Once these parameters are known, the model can be used for any spacing between the injecting and sensing contacts and for different contact geometries. The model is validated with measurements for a lightly doped substrate with a buried layer and predicts the substrate resistance values to within 12%. The substrate resistances obtained using the model are also in close agreement with the three-dimensional simulations for a lightly doped substrate

Inductors in high-performance silicon radio frequency integrated circuits : analysis, modeling, and design considerations

Spiral inductors are a key component of mixed-signal and analog integrated circuits (IC's). Such circuits are often fabricated using silicon-based technology, owing to the inherent low-cost and high volume production aspects. However, semiconducting substrate materials such as silicon can have adverse effects on spiral inductor performance due to the lossy nature of the material. Since the operating requirements of many high performance IC's demand reactive components that have high Quality Factor's (Q's), and are thus low loss devices, the need for accurate modeling of such structures over lossy substrate media is key to successful circuit design. The Q's of commonly available off-chip inductors are in the range of 50- 100 for frequencies ranging up to a few gigahertz. Since off-chip inductors must be connected through package pins, solder bumps, etc., which all contribute additional loss and thus lower the apparent Q of an external device, the typical on-chip Q requirement for a given RFIC design is generally lower than that for an off-chip spiral solution. However, a spiral inductor that was designed and fabricated originally in a low loss technology such as thin-film alumina may have substantially worse performance in regard to Q if it is used in a silicon-based technology, owing to the conductive substrate. For this reason, it is imperative that semiconducting substrate effects be accurately accounted for by any modeling effort for monolithic spirals in RFICs. This thesis presents a complete modeling solution for both single and multi-level spiral inductors over lossy silicon substrates, along with design considerations and methods for mitigation of the undesirable performance effects of semiconducting substrates. The modeling solution is based on Spectral Domain Approach (SDA) solutions for frequency dependent complex capacitive (i.e. both capacitance and conductance) parasitic elements combined with a quasi-magnetostatic field solution for calculation of the frequency dependent complex inductive (i.e. both inductance and resistance) terms. The effects of geometry and process variations are considered as well as the incorporation of Patterned Ground Shields (PGS) for the purpose of Q enhancement. Proposals for future extensions of this work are discussed in the concluding chapter

Dependence of VCO jitter on coupled noise

In mixed signal systems, the Phase Locked Loop (PLL) forms an integral part of the clock distribution scheme. The PLL is used to generate a local clock frequency, which is much higher than the external clock. The performance of a PLL is greatly influenced by the Voltage Controlled Oscillator (VCO). Any nonlinearity introduced by the VCO affects the synchronization between operation of on-chip circuitry and the external components. The jitter or phase noise of a VCO is the most important non-ideality. Phase noise or jitter becomes critical as system frequency increases. The source of timing error maybe due to various noise sources, with power supply noise and that due to substrate coupling being the major contributors. The thesis presented here deals with the effect of these two noise sources on the time period of the VCO. The peak cycle jitter and cycle-to- cycle jitter due to noise is estimated by developing a relation between the noise source and the deviation in the output voltage in terms of the circuit parameters. First crossing theory approximation has been used to convert the voltage error to timing error. The theory has been extended to analyze the timing error when the two noise sources are present together. Good agreement has been shown between the theoretical prediction and the simulated result. The analysis can be extended to any number of stages for any operating frequency as will be demonstrated in the subsequent chapters

Embedded passives in a multilayer medium

Recent advances in high density low cost RF and microwave three dimensional integration technologies using LTCC(Low Temperature Cofired Ceramics), laminate and other multilayer hybrid and integrated circuits have increased interest in the design of embedded passive components such as inductors, capacitors and filters. The purpose of this study is to develop the design methodology of multilayer components such as coupled line filters in a multilevel inhomogeneous medium. Although multilayer assembly including simple components have been used in the past for digital and low frequency systems, RF and microwave circuits have been fabricated mostly in single level configurations. The use of multilayer three dimensional components and circuits makes microwave circuits more compact and the design more flexible. This thesis describes the basic principles and computational procedure for the design of multilayer components such as, planar single and two-level spirals for applications as an inductive elements for RF and MICs, and coupled line band-pass filter circuits consisting of multiple sections. It is shown that both the quality factor and the inductance values can be enhanced by using multilevel spirals. Design methodology for general multisection filter consisting of asymmetric and multiple coupled lines is formulated and presented. It is shown that given the filter specifications, e.g., bandwidth, selectivity, input and output impedances, single, two and multilevel coupled line filters can be physically realized. The design procedure for narrow band filters is formulated in the conventional manner by using the equivalent circuit with admittance inverters and the component values of the low-pass prototype for Butterworth, Chebyshev and other response functions. Examples of Butterworth and Chebyshev multisection filters are included to demonstrate the design procedure. The physical multilevel filter is then optimized by using the SPICE model for coupled multiconductor lines on commercial CAD tool like LIBRA. The optimized multilevel structure design has been validated by MOMENTUM commercial electromagnetic simulator tool. The design methodology is validated by comparing the theoretical results with measurement data for a strip line filter fabricated on FR-4