Tensor Computation: A New Framework for High-Dimensional Problems in EDA

Many critical EDA problems suffer from the curse of dimensionality, i.e. the very fast-scaling computational burden produced by large number of parameters and/or unknown variables. This phenomenon may be caused by multiple spatial or temporal factors (e.g. 3-D field solvers discretizations and multi-rate circuit simulation), nonlinearity of devices and circuits, large number of design or optimization parameters (e.g. full-chip routing/placement and circuit sizing), or extensive process variations (e.g. variability/reliability analysis and design for manufacturability). The computational challenges generated by such high dimensional problems are generally hard to handle efficiently with traditional EDA core algorithms that are based on matrix and vector computation. This paper presents "tensor computation" as an alternative general framework for the development of efficient EDA algorithms and tools. A tensor is a high-dimensional generalization of a matrix and a vector, and is a natural choice for both storing and solving efficiently high-dimensional EDA problems. This paper gives a basic tutorial on tensors, demonstrates some recent examples of EDA applications (e.g., nonlinear circuit modeling and high-dimensional uncertainty quantification), and suggests further open EDA problems where the use of tensor computation could be of advantage.Comment: 14 figures. Accepted by IEEE Trans. CAD of Integrated Circuits and System

Interpolation-based parameterized model order reduction of delayed systems

Three-dimensional electromagnetic methods are fundamental tools for the analysis and design of high-speed systems. These methods often generate large systems of equations, and model order reduction (MOR) methods are used to reduce such a high complexity. When the geometric dimensions become electrically large or signal waveform rise times decrease, time delays must be included in the modeling. Design space optimization and exploration are usually performed during a typical design process that consequently requires repeated simulations for different design parameter values. Efficient performing of these design activities calls for parameterized model order reduction (PMOR) methods, which are able to reduce large systems of equations with respect to frequency and other design parameters of the circuit, such as layout or substrate features. We propose a novel PMOR method for neutral delayed differential systems, which is based on an efficient and reliable combination of univariate model order reduction methods, a procedure to find scaling and frequency shifting coefficients and positive interpolation schemes. The proposed scaling and frequency shifting coefficients enhance and improve the modeling capability of standard positive interpolation schemes and allow accurate modeling of highly dynamic systems with a limited amount of initial univariate models in the design space. The proposed method is able to provide parameterized reduced order models passive by construction over the design space of interest. Pertinent numerical examples validate the proposed PMOR approach

Parameterized partial element equivalent circuit method for sensitivity analysis of multiport systems

This paper presents a new technique to perform parameterized sensitivity analyses of systems that depend on multiple design parameters, such as layout and substrate features. It uses the electromagnetic (EM) method called partial element equivalent circuit to compute state space matrices at a set of design space points. These EM matrices are interpolated as functions of the design parameters. The proposed interpolation scheme allows the computation of the derivatives of the matrices, which are needed to perform the sensitivity analysis. An extensive study of the required stability and passivity properties of the system involved in the parameterized sensitivity analysis is presented. Pertinent numerical results demonstrate the robustness, accuracy, and efficiency of the proposed methodology

Guaranteed passive parameterized model order reduction of the partial element equivalent circuit (PEEC) method

The decrease of IC feature size and the increase of operating frequencies require 3-D electromagnetic methods, such as the partial element equivalent circuit (PEEC) method, for the analysis and design of high-speed circuits. Very large systems of equations are often produced by 3-D electromagnetic methods. During the circuit synthesis of large-scale digital or analog applications, it is important to predict the response of the system under study as a function of design parameters, such as geometrical and substrate features, in addition to frequency (or time). Parameterized model order reduction (PMOR) methods become necessary to reduce large systems of equations with respect to frequency and other design parameters. We propose an innovative PMOR technique applicable to PEEC analysis, which combines traditional passivity-preserving model order reduction methods and positive interpolation schemes. It is able to provide parametric reduced-order models, stable, and passive by construction over a user-defined range of design parameter values. Numerical examples validate the proposed approach

Addressing Computational Complexity of High Speed Distributed Circuits Using Model Order Reduction

Advanced in the fabrication technology of integrated circuits (ICs) over the last couple of years has resulted in an unparalleled expansion of the functionality of microelectronic systems. Today’s ICs feature complex deep-submicron mixed-signal designs and have found numerous applications in industry due to their lower manufacturing costs and higher performance levels. The tendency towards smaller feature sizes and increasing clock rates is placing higher demands on signal integrity design by highlighting previously negligible interconnect effects such as distortion, reflection, ringing, delay, and crosstalk. These effects if not predicted in the early stages of the design cycle can severely degrade circuit performance and reliability. The objective of this thesis is to develop new model order reduction (MOR) techniques to minimize the computational complexity of non-linear circuits and electronic systems that have delay elements. MOR techniques provide a mechanism to generate reduced order models from the detailed description of the original modified nodal analysis (MNA) formulation. The following contributions are made in this thesis: 1. The first project presents a methodology for reduction of Partial Element Equivalent Circuit (PEEC) models. PEEC method is widely used in electromagnetic compatibility and signal integrity problems in both the time and frequency domains. The PEEC model with retardation has been applied to 3-D analysis but often result in large and dense matrices, which are computationally expensive to solve. In this thesis, a new moment matching technique based on Multi-order Arnoldi is described to model PEEC networks with retardation. 2. The second project deals with developing an efficient model order reduction algorithm for simulating large interconnect networks with nonlinear elements. The proposed methodology is based on a multidimensional subspace method and uses constraint equations to link the nonlinear elements and biasing sources to the reduced order model. This approach significantly improves the simulation time of distributed nonlinear systems, since additional ports are not required to link the nonlinear elements to the reduced order model, yielding appreciable savings in the size of the reduced order model and computational time. 3. A parameterized reduction technique for nonlinear systems is presented. The proposed method uses multidimensional subspace and variational analysis to capture the variances of design parameters and approximates the weakly nonlinear functions as a Taylor series. An SVD approach is presented to address the efficiency of reduced order model. The proposed methodology significantly improves the simulation time of weakly nonlinear systems since the size of the reduced system is smaller than the original system and a new reduced model is not required each time a design parameter is changed

Delay Extraction based Macromodeling with Parallel Processing for Efficient Simulation of High Speed Distributed Networks

This thesis attempts to address the computational demands of accurate modeling of high speed distributed networks such as interconnect networks and power distribution networks. In order to do so, two different approaches towards modeling of high speed distributed networks are considered. One approach deals with cases where the physical characteristics of the network are not known and the network is characterized by its frequency domain tabulated data. Such examples include long interconnect networks described by their Y parameter data. For this class of problems, a novel delay extraction based IFFT algorithm has been developed for accurate transient response simulation. The other modeling approach is based on a detailed knowledge of the physical and electrical characteristics of the network and assuming a quasi transverse mode of propagation of the electromagnetic wave through the network. Such problems may include two dimensional (2D) and three dimensional (3D) power distribution networks with known geometry and materials. For this class of problem, a delay extraction based macromodeling approaches is proposed which has been found to be able to capture the distributed effects of the network resulting in more compact and accurate simulation compared to the state-of-the-art quasi-static lumped models. Furthermore, waveform relaxation based algorithms for parallel simulations of large interconnect networks and 2D power distribution networks is also presented. A key contribution of this body of work is the identification of naturally parallelizable and convergent iterative techniques that can divide the computational costs of solving such large macromodels over a multi-core hardware

Stochastic Testing Simulator for Integrated Circuits and MEMS: Hierarchical and Sparse Techniques

Process variations are a major concern in today's chip design since they can significantly degrade chip performance. To predict such degradation, existing circuit and MEMS simulators rely on Monte Carlo algorithms, which are typically too slow. Therefore, novel fast stochastic simulators are highly desired. This paper first reviews our recently developed stochastic testing simulator that can achieve speedup factors of hundreds to thousands over Monte Carlo. Then, we develop a fast hierarchical stochastic spectral simulator to simulate a complex circuit or system consisting of several blocks. We further present a fast simulation approach based on anchored ANOVA (analysis of variance) for some design problems with many process variations. This approach can reduce the simulation cost and can identify which variation sources have strong impacts on the circuit's performance. The simulation results of some circuit and MEMS examples are reported to show the effectiveness of our simulatorComment: Accepted to IEEE Custom Integrated Circuits Conference in June 2014. arXiv admin note: text overlap with arXiv:1407.302