Toward Reliable, Secure, and Energy-Efficient Multi-Core System Design

Computer hardware researchers have perennially focussed on improving the performance of computers while stipulating the energy consumption under a strict budget. While several innovations over the years have led to high performance and energy efficient computers, more challenges have also emerged as a fallout. For example, smaller transistor devices in modern multi-core systems are afflicted with several reliability and security concerns, which were inconceivable even a decade ago. Tackling these bottlenecks happens to negatively impact the power and performance of the computers. This dissertation explores novel techniques to gracefully solve some of the pressing challenges of the modern computer design. Specifically, the proposed techniques improve the reliability of on-chip communication fabric under a high power supply noise, increase the energy-efficiency of low-power graphics processing units, and demonstrate an unprecedented security loophole of the low-power computing paradigm through rigorous hardware-based experiments

A survey of scan-capture power reduction techniques

With the advent of sub-nanometer geometries, integrated circuits (ICs) are required to be checked for newer defects. While scan-based architectures help detect these defects using newer fault models, test data inflation happens, increasing test time and test cost. An automatic test pattern generator (ATPG) exercise’s multiple fault sites simultaneously to reduce test data which causes elevated switching activity during the capture cycle. The switching activity results in an IR drop exceeding the devices under test (DUT) specification. An increase in IR-drop leads to failure of the patterns and may cause good DUTs to fail the test. The problem is severe during at-speed scan testing, which uses a functional rated clock with a high frequency for the capture operation. Researchers have proposed several techniques to reduce capture power. They used various methods, including the reduction of switching activity. This paper reviews the recently proposed techniques. The principle, algorithm, and architecture used in them are discussed, along with key advantages and limitations. In addition, it provides a classification of the techniques based on the method used and its application. The goal is to present a survey of the techniques and prepare a platform for future development in capture power reduction during scan testing

Cross-Layer Resiliency Modeling and Optimization: A Device to Circuit Approach

The never ending demand for higher performance and lower power consumption pushes the VLSI industry to further scale the technology down. However, further downscaling of technology at nano-scale leads to major challenges. Reduced reliability is one of them, arising from multiple sources e.g. runtime variations, process variation, and transient errors. The objective of this thesis is to tackle unreliability with a cross layer approach from device up to circuit level

European White Book on Real-Time Power Hardware in the Loop Testing : DERlab Report No. R- 005.0

The European White Book on Real-Time-Powerhardware-in-the-Loop testing is intended to serve as a reference document on the future of testing of electrical power equipment, with specifi c focus on the emerging hardware-in-the-loop activities and application thereof within testing facilities and procedures. It will provide an outlook of how this powerful tool can be utilised to support the development, testing and validation of specifi cally DER equipment. It aims to report on international experience gained thus far and provides case studies on developments and specifi c technical issues, such as the hardware/software interface. This white book compliments the already existing series of DERlab European white books, covering topics such as grid-inverters and grid-connected storag

Protection of Microgrids: A Scalable and Topology Agnostic Scheme With Self-Healing Dynamic Reconfiguration

Momentum towards realizing the smart grid will continue to result in high penetration of renewable fed Distributed Energy Resources (DERs) in the Electric Power System (EPS). These DERs will most likely be Inverter Based Resources(IBRs) and will be an integral part of the distribution system in the near future. The drive towards resiliency with these IBRs will enable a modular topology where several microgrids are tied together, operating synchronously to form the future EPS at the distribution level. Since the microgrids can evolve from existing distribution feeders, they will be unbalanced in load, phases, and feeder impedances. A typical control strategy of a conventional inverter that follows the grid voltage and frequency while injecting positive-sequence current can lead to undesirable performance for the unbalanced systems, especially in the islanded mode of operation. So, the dissertation will first focus on the control aspect of IBRs in an unbalanced system. Acceptable operating conditions with stability against disturbances and faults are the primary focus. For the proper functioning of these microgrids, there is a need for grid-forming inverters that can enable acceptable performance and coexist with conventional grid-following inverters that supply only positive-sequence currents. In addition to the control objectives, limiting inverter output during faulted or overload conditions with a current limiter is essential. These control objectives can be implemented in both the synchronous reference frame ($dq$ coordinates) and the natural reference frame ($abc$ coordinates). Hence a comparison study is performed to understand the merit of each implementation related to this specific topology. As 100\% IBR-based microgrid becomes an integral part of the distribution system, the issues and challenges arising from its implementation should be addressed for successful operation. Designing reliable protection is one of the significant challenges for microgrids. Most microgrid protection schemes found in published literature suffer from a lack of generality. They work well for the assumed topology, including the type and placement of sources. Other generic protection schemes tend to be too complicated, expensive, or both. To overcome these drawbacks, a topology-agnostic, scalable, and cost-aware protection based on fundamental principles is developed that works in the presence of high penetration of inverter-based resources (IBRs). The protection system includes primary and backup. It also implements stable automatic reconfiguration of the healthy sections of the system after clearance of fault, thus increasing resilience by self-healing. The scheme is validated in PSCAD for primary and backup protection and reconfiguration on the IEEE 123-node feeder in grid-connected and islanded modes with 15 IBRs connected to the system. As the designed protection scheme requires communication between protective devices and the microgrid controller, the method must be validated in real-time with cyber-physical co-simulation for a successful demonstration. In this regard, a Hardware-In-the-Loop (HIL) platform between a simulated power system model using RTDS and physical protective devices is built. In the HIL platform, the primary protection of the scheme is programmed in SEL 421-7 relay, and backup protection is programmed in MATLAB on a generic computer acting as a microgrid controller. The IEC 61850 models are used to communicate between the SEL-421-7 relay and RTDS, whereas TCP/IP communication connects the microgrid controller to RTDS. The focus of the work is to demonstrate the co-simulation platform with communication links established using both protocols and validate the proposed scheme in real-time on the IEEE 123 node distribution feeder. The IEC 61850 and TCP/IP communications configuration are discussed as the interface requires proper hardware and software setup. The real-time performance indicates the Hardware In the Loop (HIL) framework as a competent testing environment for the developed protection scheme for microgrids. In summary, a scalable and topology agnostic protection scheme with self-healing dynamic reconfiguration is developed for microgrids. Clear guidelines for implementation of the proposed scheme on any microgrid topology are also described

Probabilistic design for emerging memory and nanometer-scale logic

As semiconductor technology has scaled down, the impact of stochastic behavior in very large scale integrated circuits (VLSI) has become an ever-more important concern. This dissertation investigates two distinct classes of problems that require the use of probabilistic methods and models: (1) Modeling and exploiting stochastic behavior in advanced memory technologies; (2) Probabilistic modeling of faults due to on-chip voltage variation. This dissertation first investigates the unique physics-level stochasticity of spin-transfer torque magnetic RAM (STT-RAM). The write process of STT-RAM is stochastic: specifically, the write time of a bitcell varies significantly. The wors-tcase approach, which uses the longest write pulse duration, guarantees a successful write; however, it introduces significant energy overhead due to excessive margins since the average write pulse duration is far shorter than the worst-case pulse duration. This dissertation develops novel circuit techniques to exploit the stochastic properties of STT-RAM write operation for energy savings by moving away from the worst-case approach to dynamic strategies while maintaining the required low error rate. The first contribution is a variable energy write (VEW) architecture that effectively exploits the wide distribution of write time to greatly reduce energy via a mechanism that checks the instantaneous state of the bitcell and deactivates the write current once the correct value has registered. The second contribution is a multiple attempt write (MAW) strategy that utilizes the asymptotic temporal stochastic independence of repeated switching events to achieve a dramatic reduction in energy. The proposed architectures are evaluated using a compact STT-RAM cell model. Analysis indicates that VEW succeeded in reducing the write energy by 94.7% with approximately 1% relative area overhead under an efficient design methodology compared with the conventional designs relying on the worst case approach. MAW reduced the overall write energy by 94.6% with approximately 0.05% relative area overhead. This dissertation then addresses the problem of probabilistic modeling of faults due to on-chip voltage variations. The power supply voltage variation can increase gate delay, resulting in timing faults on near-critical paths. These low-level faults ultimately propagate to architecture and application levels, often leading to critical system failures. Developing an accurate fault model and injection tool that generates and propagates faults from circuit- to gate-level is important for accurately predicting the resulting system failures. This is challenging since the model needs to accurately capture the physical characteristics at the circuit level that define the likelihood of a fault and use that information to guide the injection with the proper probability. At the same time, the analysis and fault injections need to be computationally manageable to allow analysis of realistic systems under realistic workloads. The conventional fault models rely on either Monte Carlo sampling or time-consuming runtime simulation using the worst-case voltage drop. To overcome simulation overheads of runtime circuit-level simulation, a novel two-phase approach is proposed. The main idea is that circuit characterization can be done before simulation. The result of pre-characterization is used at runtime via a form of look-up to enable gate-level efficiency. The two-phase methodology is time-efficient but may require high memory unless the look-up tables are carefully optimized. This dissertation also develops the fault probability estimation based on workload-specific voltage distribution, rather than a fixed worst-case voltage. The proposed methodology is implemented on an OpenSPARC design targeting on a 32nm technology node. Analysis indicates the proposed fault modeling and injection flow reduces runtime overhead by 24X compared to the previously best-known gate-level fault simulator while having circuit level accuracy.Electrical and Computer Engineerin

Fault Prognosis in Particle Accelerator Power Electronics Using Ensemble Learning

Early fault detection and fault prognosis are crucial to ensure efficient and safe operations of complex engineering systems such as the Spallation Neutron Source (SNS) and its power electronics (high voltage converter modulators). Following an advanced experimental facility setup that mimics SNS operating conditions, the authors successfully conducted 21 fault prognosis experiments, where fault precursors are introduced in the system to a degree enough to cause degradation in the waveform signals, but not enough to reach a real fault. Nine different machine learning techniques based on ensemble trees, convolutional neural networks, support vector machines, and hierarchical voting ensembles are proposed to detect the fault precursors. Although all 9 models have shown a perfect and identical performance during the training and testing phase, the performance of most models has decreased in the prognosis phase once they got exposed to real-world data from the 21 experiments. The hierarchical voting ensemble, which features multiple layers of diverse models, maintains a distinguished performance in early detection of the fault precursors with 95% success rate (20/21 tests), followed by adaboost and extremely randomized trees with 52% and 48% success rates, respectively. The support vector machine models were the worst with only 24% success rate (5/21 tests). The study concluded that a successful implementation of machine learning in the SNS or particle accelerator power systems would require a major upgrade in the controller and the data acquisition system to facilitate streaming and handling big data for the machine learning models. In addition, this study shows that the best performing models were diverse and based on the ensemble concept to reduce the bias and hyperparameter sensitivity of individual models.Comment: 25 Pages, 13 Figures, 5 Table

Langley aerospace test highlights, 1985

The role of the Langley Research Center is to perform basic and applied research necessary for the advancement of aeronautics and space flight, to generate new and advanced concepts for the accomplishment of related national goals, and to provide research advice, technological support, and assistance to other NASA installations, other government agencies, and industry. Significant tests which were performed during calendar year 1985 in Langley test facilities, are highlighted. Both the broad range of the research and technology activities at the Langley Research Center and the contributions of this work toward maintaining United States leadership in aeronautics and space research, are illustrated. Other highlights of Langley research and technology for 1985 are described in Research and Technology-1985 Annual Report of the Langley Research Center

Measurement-Based Monitoring and Control in Power Systems with High Renewable Penetrations

Power systems are experiencing rapid changes in their generation mixes because of the increasing integration of inverter-based resources (IBRs) and the retirement of traditional generations. This opens opportunities for a cleaner energy outlook but also poses challenges to the safe operation of the power networks. Enhanced monitoring and control based on the increasingly available measurements are essential in assisting stable operation and effective planning for these evolving systems. First, awareness of the evolving dynamic characteristics is quintessential for secure operation and corrective planning. A quantified monitoring study that keeps track of the inertial response and primary frequency response is conducted on the Eastern Interconnection (EI) for the past decade with field data. Whereas the inertia declined by at least 10%, the primary frequency response experienced an unexpected increase. The findings unveiled in the trending analysis also led to an improved event MW size estimation method, as well as discussions about regional dynamics. Experiencing a faster and deeper renewable integration, the Continental Europe Synchronous Area (CESA) system has been threatened by more frequent occurrences of inter-area oscillations during light-load high-renewable periods. A measurement-based oscillation damping control scheme is proposed for CESA with reduced reliance on system models. The design, implementation, and hardware-in-the-loop (HIL) testing of the controller are discussed in detail. Despite the challenges, the increasing presence of IBRs also brings opportunities for fast and efficient controls. Together with synchronized measurement, IBRs have the potential to flexibly complement traditional frequency and voltage control schemes for improved frequency and voltage recovery. The design, implementation, and HIL testing of the measurement-based frequency and voltage control for the New York State Grid are presented. In addition to the transmission level development, IBRs deployed in distribution networks can also be valuable assets in emergency islanding situations if controlled properly. A power management module is proposed to take advantage of measurements and automatically control the electric boundaries of islanded microgrids for maximized power utilization and improved frequency regulation. The module is designed to be adaptive to arbitrary non-meshed topologies with multiple source locations for increased flexibility, expedited deployment, and reduced cost