Robust simulation methodology for surface-roughness loss in interconnect and package modelings

In multigigahertz integrated-circuit design, the extra energy loss caused by conductor surface roughness in metallic interconnects and packagings is more evident than ever before and demands explicit consideration for accurate prediction of signal integrity and energy consumption. Existing techniques based on analytical approximation, despite simple formulations, suffer from restrictive valid ranges, namely, either small or large roughness/frequencies. In this paper, we propose a robust and efficient numerical-simulation methodology applicable to evaluating general surface roughness, described by parameterized stochastic processes, across a wide frequency band. Traditional computation-intensive electromagnetic simulation is avoided via a tailored scalar-wave modeling to capture the power loss due to surface roughness. The spectral stochastic collocation method is applied to construct the complete statistical model. Comparisons with full wave simulation as well as existing methods in their respective valid ranges then verify the effectiveness of the proposed approach. © 2009 IEEE.published_or_final_versio

An effective modeling framework for the analysis of interconnects subject to line-edge roughness

This letter proposes a complete and efficient simulation framework to assess the effects of line-edge roughness appearing in on-chip lines. The modeling approach consists of three steps. First, a stochastic macromodel is created for the per-unit-length RLGC parameters of the line. Secondly, random conductor edge profiles are generated using randomized splines. These are combined with the stochastic macromodel to readily provide place-dependent RLGC parameters. Finally, the resulting nonuniform transmission line is analyzed by means of a fast and accurate perturbation technique. To validate the proposed approach, a statistical analysis of the response of a coupled inverted embedded microstrip line is carried out for different roughness parameters

Power distribution network inductance calculation, transient current measurement and conductor surface roughness extraction

The first part in the thesis discussed the modeling of the mid-frequency inductance for Zpp type plane pairs in power distribution networks (PDN). It is a key step for the placement of the decoupling capacitors. This paper gives an efficient approach for the calculation of the inductance for different capacitor placements. The PEEC based formulations takes advantage of the opposite currents in the planes. This leads to compute time reductions and memory savings for both the element calculation and the matrix solve step. A formulation is used where placement of capacitors leads to only small changes in the circuit matrix. Comparisons with other models are made to validate our results. In the second part, the application of GMI probe to measure IC switching current. IC switching current is the main noise source of many power integrity issues in printed circuit boards. Accurate measurement of the current waveforms is critical for an effective power distribution network design. In this paper, using a giant magneto-impedance (GMI) probe for this purpose is studied. A side-band detection and demodulation system is built up to measure various time-domain waveforms using an oscilloscope. It is found that the GMI probes are potentially suitable for this kind of time-domain measurements, but probe designs and measurement setups need further improvements for this application. In the third part, the new Sigma rule to evaluate parameters of copper surface roughness in PCB layers is presented. This approach is based on taking SEM images of PCB cross-sections. The approach is automat [sic] zed [sic] by applying image processing tools and Matlab code to evaluate average roughness amplitude and period of roughness function. This information could be used in numerical and analytical modeling, as well as in the DERM method to separate rough conductor loss from dielectric loss --Abstract, page iv

Frequency- and time-domain analysis of high-frequency on-chip interconnects with nonuniform conductor edges

In this paper we illustrate a modeling framework to analyze on-chip transmission lines affected by longitudinal nonuniformities in their conductor edges. The method consists of two steps. First, a macromodel for the frequency-dependent per-unit-length parameters is constructed based on an accurate field solver and it is used to conveniently obtain the pertinent place-dependent line parameters. Second, a fast and accurate perturbation technique is used to analyze the nonuniform transmission line problem. As shown by the application example, the proposed technique makes the statistical assessment for a large number of edge profiles feasible. Numerical results and discussions are provided for the case of an on-chip inverted embedded microstrip line

Efficient integral equation based algorithms for parasitic extraction of interconnects with smooth or rough surface

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Includes bibliographical references (p. 187-198).This thesis describes a few efficient parasitic extraction algorithms based on integral equation methods. It has two parts. Part one describes the algorithms used in FastImp, a program for accurate analysis of wide-band electromagnetic effects in very complicated geometries of conductors. The program is based on a recently developed surface integral formulation and a Pre-corrected FFT accelerated iterative method, but includes a new piecewise quadrature panel integration scheme, a new scaling and preconditioning technique as well as a generalized grid interpolation and projection strategy. Computational results are given on a variety of integrated circuit interconnect structures to demonstrate that FastImp is robust and can accurately analyze very complicated geometries of conductors. Part two describes an efficient Stochastic Integral Equation (SIE) Method for computing the mean value and variance of the capacitance of interconnects with random surface roughness in O(Nlog2Ì(N)) time. An ensemble average Green's function is used to account for the surface roughness. A second-order correction scheme is used to improve the accuracy. A sparsification technique based on the Hierarchical Matrix method is proposed to significantly reduce the computational cost. The SIE method avoids the time-consuming Monte Carlo simulations and the discretization of rough surfaces. Numerical experiments show that the results of the new method agree very well with those of Monte Carlo simulations.by Zhenhai Zhu.Ph.D

Measurements and simulation of conductor-related loss of PCB transmission lines

With continuously increasing data rates Signal Integrity (SI) problems become more and more challenging. One of the main issues in high-speed data transfer is the frequency-dependent loss of transmission lines. This thesis is dedicated to conductor-related loss mechanisms in printed circuit board (PCB) transmission lines. This thesis provides the experimental investigation of conductor properties used for fabrication of PCBs. Particularly, the resistivity and conductivity along with the temperature coefficients of eleven copper types is measured and reported. A four probe measurement technique is used. Results were verified by two independent measurements and show discrepancy of less than 0.5%. Another major conductor-related loss mechanism is the attenuation of the electromagnetic waves due to the surface roughness of PCB conductors. There are several models attempting to take into account the roughness effect. However none of them are able to explain or predict the transmission line behavior with high accuracy. Particularly, the experimental observations show that the slope of S21 curves increases with frequency, which cannot be modelled by the existing model. To better understand the physics associated with the loss due to the surface roughness of conductors, and be able to predict the behavior of transmission lines in the future, a full wave model of surface roughness was developed. The detailed methodology for 3D roughness generation is provided --Abstract, page iii

Field solver technologies for variation-aware interconnect parasitic extraction

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.Cataloged from PDF version of thesis.Includes bibliographical references (p. 207-213).Advances in integrated circuit manufacturing technologies have enabled high density onchip integration by constantly scaling down the device and interconnect feature size. As a consequence of the ongoing technology scaling (from 45nm to 32nm, 22nm and beyond), geometrical variabilities induced by the uncertainties in the manufacturing processes are becoming more significant. Indeed, the dimensions and shapes of the manufactured devices and interconnect structures may vary by up to 40% from their design intent. The effect of such variabilities on the electrical characteristics of both devices and interconnects must be accurately evaluated and accounted for during the design phase. In the last few years, there have been several attempts to develop variation-aware extraction algorithms, i.e. algorithms that evaluate the effect of geometrical variabilities on the electrical characteristics of devices and interconnects. However, most algorithms remain computationally very expensive. In this thesis the focus is on variation-aware interconnect parasitic extraction. In the first part of the thesis several discretization-based variation-aware solver techniques are developed. The first technique is a stochastic model reduction algorithm (SMOR) The SMOR guarantees that the statistical moments computed from the reduced model are the same as those of the full model. The SMOR works best for problems in which the desired electrical property is contained in an easily defined subspace.(cont.) The second technique is the combined Neumann Hermite expansion (CNHE). The CNHE combines the advantages of both the standard Neumann expansion and the standard stochastic Galerkin method to produce a very efficient extraction algorithm. The CNHE works best in problems for which the desired electrical property (e.g. impedance) is accurately expanded in terms of a low order multivariate Hermite expansion. The third technique is the stochastic dominant singular vectors method (SDSV). The SDSV uses stochastic optimization in order to sequentially determine an optimal reduced subspace, in which the solution can be accurately represented. The SDSV works best for large dimensional problems, since its complexity is almost independent of the size of the parameter space. In the second part of the thesis, several novel discretization-free variation aware extraction techniques for both resistance and capacitance extraction are developed. First we present a variation-aware floating random walk (FRW) to extract the capacitance/resistance in the presence of non-topological (edge-defined) variations. The complexity of such algorithm is almost independent of the number of varying parameters. Then we introduce the Hierarchical FRW to extract the capacitance/resistance of a very large number of topologically different structures, which are all constructed from the same set of building blocks. The complexity of such algorithm is almost independent of the total number of structures. All the proposed techniques are applied to a variety of examples, showing orders of magnitude reduction in the computational time compared to the standard approaches. In addition, we solve very large dimensional examples that are intractable when using standard approaches.by Tarek Ali El-Moselhy.Ph.D

Enabling Technologies for 3D ICs: TSV Modeling and Analysis

Through silicon via (TSV) based three-dimensional (3D) integrated circuit (IC) aims to stack and interconnect dies or wafers vertically. This emerging technology offers a promising near-term solution for further miniaturization and the performance improvement of electronic systems and follows a more than Moore strategy. Along with the need for low-cost and high-yield process technology, the successful application of TSV technology requires further optimization of the TSV electrical modeling and design. In the millimeter wave (mmW) frequency range, the root mean square (rms) height of the TSV sidewall roughness is comparable to the skin depth and hence becomes a critical factor for TSV modeling and analysis. The impact of TSV sidewall roughness on electrical performance, such as the loss and impedance alteration in the mmW frequency range, is examined and analyzed following the second order small perturbation method. Then, an accurate and efficient electrical model for TSVs has been proposed considering the TSV sidewall roughness effect, the skin effect, and the metal oxide semiconductor (MOS) effect. However, the emerging application of 3D integration involves an advanced bio-inspired computing system which is currently experiencing an explosion of interest. In neuromorphic computing, the high density membrane capacitor plays a key role in the synaptic signaling process, especially in a spike firing analog implementation of neurons. We proposed a novel 3D neuromorphic design architecture in which the redundant and dummy TSVs are reconfigured as membrane capacitors. This modification has been achieved by taking advantage of the metal insulator semiconductor (MIS) structure along the sidewall, strategically engineering the fixed oxide charges in depletion region surrounding the TSVs, and the addition of oxide layer around the bump without changing any process technology. Without increasing the circuit area, these reconfiguration of TSVs can result in substantial power consumption reduction and a significant boost to chip performance and efficiency. Also, depending on the availability of the TSVs, we proposed a novel CAD framework for TSV assignments based on the force-directed optimization and linear perturbation

Wideband characterization of printed circuit board materials up to 50 GHz

A traveling-wave technique developed a few years ago in the Missouri S&T EMC Laboratory has been employed until now for characterization of PCB materials over a broad frequency range up to 30 GHz. This technique includes measuring S-parameters of the specially designed PCB test vehicles. An extension of the frequency range of printed circuit board laminate dielectric and copper foil characterization is an important problem. In this work, a new PCB test vehicle design for operating up to 50 GHz has been proposed. As the frequency range of measurements increases, the analysis of errors and uncertainties in measuring dielectric properties becomes increasingly important. Formulas for quantification of two major groups of errors, repeatability (manufacturing variability) and reproducibility (systematic) errors, in extracting dielectric constant (DK) and dissipation factor (DK) have been derived, and computations for a number of cases are presented. Conductor (copper foil) surface roughness of PCB interconnects is an important factor, which affects accuracy of DK and DF measurements. This work describes a new algorithm for semi-automatic characterization of copper foil profiles on optical or scanning electron microscopy (SEM) pictures of signal traces. The collected statistics of numerous copper foil roughness profiles allows for introducing a new metric for roughness characterization of PCB interconnects. This is an important step to refining the measured DK and DF parameters from roughness contributions. The collected foil profile data and its analysis allow for developing design curves , which could be used by SI engineers and electronics developers in their designs --Abstract, page iii