305 research outputs found

    Efficient integral equation based algorithms for parasitic extraction of interconnects with smooth or rough surface

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    Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Includes bibliographical references (p. 187-198).This thesis describes a few efficient parasitic extraction algorithms based on integral equation methods. It has two parts. Part one describes the algorithms used in FastImp, a program for accurate analysis of wide-band electromagnetic effects in very complicated geometries of conductors. The program is based on a recently developed surface integral formulation and a Pre-corrected FFT accelerated iterative method, but includes a new piecewise quadrature panel integration scheme, a new scaling and preconditioning technique as well as a generalized grid interpolation and projection strategy. Computational results are given on a variety of integrated circuit interconnect structures to demonstrate that FastImp is robust and can accurately analyze very complicated geometries of conductors. Part two describes an efficient Stochastic Integral Equation (SIE) Method for computing the mean value and variance of the capacitance of interconnects with random surface roughness in O(Nlog2Ì(N)) time. An ensemble average Green's function is used to account for the surface roughness. A second-order correction scheme is used to improve the accuracy. A sparsification technique based on the Hierarchical Matrix method is proposed to significantly reduce the computational cost. The SIE method avoids the time-consuming Monte Carlo simulations and the discretization of rough surfaces. Numerical experiments show that the results of the new method agree very well with those of Monte Carlo simulations.by Zhenhai Zhu.Ph.D

    Polynomial chaos based uncertainty quantification for stochastic electromagnetic scattering problems

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    Field solver technologies for variation-aware interconnect parasitic extraction

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    Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.Cataloged from PDF version of thesis.Includes bibliographical references (p. 207-213).Advances in integrated circuit manufacturing technologies have enabled high density onchip integration by constantly scaling down the device and interconnect feature size. As a consequence of the ongoing technology scaling (from 45nm to 32nm, 22nm and beyond), geometrical variabilities induced by the uncertainties in the manufacturing processes are becoming more significant. Indeed, the dimensions and shapes of the manufactured devices and interconnect structures may vary by up to 40% from their design intent. The effect of such variabilities on the electrical characteristics of both devices and interconnects must be accurately evaluated and accounted for during the design phase. In the last few years, there have been several attempts to develop variation-aware extraction algorithms, i.e. algorithms that evaluate the effect of geometrical variabilities on the electrical characteristics of devices and interconnects. However, most algorithms remain computationally very expensive. In this thesis the focus is on variation-aware interconnect parasitic extraction. In the first part of the thesis several discretization-based variation-aware solver techniques are developed. The first technique is a stochastic model reduction algorithm (SMOR) The SMOR guarantees that the statistical moments computed from the reduced model are the same as those of the full model. The SMOR works best for problems in which the desired electrical property is contained in an easily defined subspace.(cont.) The second technique is the combined Neumann Hermite expansion (CNHE). The CNHE combines the advantages of both the standard Neumann expansion and the standard stochastic Galerkin method to produce a very efficient extraction algorithm. The CNHE works best in problems for which the desired electrical property (e.g. impedance) is accurately expanded in terms of a low order multivariate Hermite expansion. The third technique is the stochastic dominant singular vectors method (SDSV). The SDSV uses stochastic optimization in order to sequentially determine an optimal reduced subspace, in which the solution can be accurately represented. The SDSV works best for large dimensional problems, since its complexity is almost independent of the size of the parameter space. In the second part of the thesis, several novel discretization-free variation aware extraction techniques for both resistance and capacitance extraction are developed. First we present a variation-aware floating random walk (FRW) to extract the capacitance/resistance in the presence of non-topological (edge-defined) variations. The complexity of such algorithm is almost independent of the number of varying parameters. Then we introduce the Hierarchical FRW to extract the capacitance/resistance of a very large number of topologically different structures, which are all constructed from the same set of building blocks. The complexity of such algorithm is almost independent of the total number of structures. All the proposed techniques are applied to a variety of examples, showing orders of magnitude reduction in the computational time compared to the standard approaches. In addition, we solve very large dimensional examples that are intractable when using standard approaches.by Tarek Ali El-Moselhy.Ph.D

    Advanced Electromagnetic Numerical Modeling Techniques for Various Periodic and Quasi-Periodic Systems

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    This dissertation is mainly concerned with several advanced electromagnetic modeling techniques for practical complex systems, which involve periodic analyses. The focus is to reveal the physics of the electromagnetic wave interaction with the complex structures, and also to arrive at improved computational algorithms. This dissertation consists of three self-contained parts, each discussing one modeling technique. Examples presented in this dissertation include (a) an analysis of conductor surface-roughness effects, (b) a novel model for vertical interconnects (vias) and (c) a leaky-wave study of a Fabry-Perot resonant cavity antenna. The first part investigates conductor surface roughness effects for stripline. An equivalent rough-surface-impedance is extracted using a periodic full-wave analysis and is then used for the modification of the transmission line per-unit-length parameter. The second part proposes a semi-analytical analysis for massively-coupled vias with arbitrarily-shaped antipads, based on the reciprocity theorem. The use of reciprocity yields simple design formulas and is seen to greatly improve the computational efficiency, due to the fast-converging mode-matching calculation. The third part presents a leaky-wave study of a Fabry-Perot cavity antenna made from a patch array. The patch current densities are calculated using the array scanning method. Based on this, a "leaky-wave current" is defined and calculated using residue integration. In addition, the radiation properties of a large finite-size array (truncation effects) are evaluated. All three proposed models are verified by full-wave simulations and/or measurements. Numerical results prove the effectiveness and accuracy of these models.Electrical and Computer Engineering, Department o

    Full-wave analysis of large conductor systems over substrate

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    Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (leaves 137-145).Designers of high-performance integrated circuits are paying ever-increasing attention to minimizing problems associated with interconnects such as noise, signal delay, crosstalk, etc., many of which are caused by the presence of a conductive substrate. The severity of these problems increases as integrated circuit clock frequencies rise into the multiple gigahertz range. In this thesis, a simulation tool is presented for the extraction of full-wave interconnect impedances in the presence of a conducting substrate. The substrate effects are accounted for through the use of full-wave layered Green's functions in a mixed-potential integral equation (MPIE) formulation. Particularly, the choice of implementation for the layered Green's function kernels motivates the development of accelerated techniques for both their 3D volume and 2D surface integrations, where each integration type can be reduced to a sum of D line integrals. In addition, a set of high-order, frequency-independent basis functions is developed with the ability to parameterize the frequency-dependent nature of the solution space, hence reducing the number of unknowns required to capture the interconnects' frequency-variant behavior.(cont.) Moreover, a pre-corrected FFT acceleration technique, conventional for the treatment of scalar Green's function kernels, is extended in the solver to accommodate the dyadic Green's function kernels encountered in the substrate modeling problem. Overall, the integral-equation solver, combined with its numerous acceleration techniques, serves as a viable solution to full-wave substrate impedance extractions of large and complex interconnect structures.by Xin Hu.Ph.D

    Combined fast multipole-QR compression technique for solving electrically small to large structures for broadband applications

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    An approach that efficiently solves for a desired parameter of a system or device that can include both electrically large fast multipole method (FMM) elements, and electrically small QR elements. The system or device is setup as an oct-tree structure that can include regions of both the FMM type and the QR type. An iterative solver is then used to determine a first matrix vector product for any electrically large elements, and a second matrix vector product for any electrically small elements that are included in the structure. These matrix vector products for the electrically large elements and the electrically small elements are combined, and a net delta for a combination of the matrix vector products is determined. The iteration continues until a net delta is obtained that is within predefined limits. The matrix vector products that were last obtained are used to solve for the desired parameter

    Design automation and analysis of three-dimensional integrated circuits

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    Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Includes bibliographical references (p. 165-176).This dissertation concerns the design of circuits and systems for an emerging technology known as three-dimensional integration. By stacking individual components, dice, or whole wafers using a high-density electromechanical interconnect, three-dimensional integration can achieve scalability and performance exceeding that of conventional fabrication technologies. There are two main contributions of this thesis. The first is a computer-aided design flow for the digital components of a three-dimensional integrated circuit (3-D IC). This flow primarily consists of two software tools: PR3D, a placement and routing tool for custom 3-D ICs based on standard cells, and 3-D Magic, a tool for designing, editing, and testing physical layout characteristics of 3-D ICs. The second contribution of this thesis is a performance analysis of the digital components of 3-D ICs. We use the above tools to determine the extent to which 3-D integration can improve timing, energy, and thermal performance. In doing so, we verify the estimates of stochastic computational models for 3-D IC interconnects and find that the models predict the optimal 3-D wire length to within 20% accuracy. We expand upon this analysis by examining how 3-D technology factors affect the optimal wire length that can be obtained. Our ultimate analysis extends this work by directly considering timing and energy in 3-D ICs. In all cases we find that significant performance improvements are possible. In contrast, thermal performance is expected to worsen with the use of 3-D integration. We examine precisely how thermal behavior scales in 3-D integration and determine quantitatively how the temperature may be controlled during the circuit placement process. We also show how advanced packaging(cont.) technologies may be leveraged to maintain acceptable die temperatures in 3-D ICs. Finally, we explore two issues for the future of 3-D integration. We determine how technology scaling impacts the effect of 3-D integration on circuit performance. We also consider how to improve the performance of digital components in a mixed-signal 3-D integrated circuit. We conclude with a look towards future 3-D IC design tools.by Shamik Das.Ph.D

    Microfluidics and Nanofluidics Handbook

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    The Microfluidics and Nanofluidics Handbook: Two-Volume Set comprehensively captures the cross-disciplinary breadth of the fields of micro- and nanofluidics, which encompass the biological sciences, chemistry, physics and engineering applications. To fill the knowledge gap between engineering and the basic sciences, the editors pulled together key individuals, well known in their respective areas, to author chapters that help graduate students, scientists, and practicing engineers understand the overall area of microfluidics and nanofluidics. Topics covered include Finite Volume Method for Numerical Simulation Lattice Boltzmann Method and Its Applications in Microfluidics Microparticle and Nanoparticle Manipulation Methane Solubility Enhancement in Water Confined to Nanoscale Pores Volume Two: Fabrication, Implementation, and Applications focuses on topics related to experimental and numerical methods. It also covers fabrication and applications in a variety of areas, from aerospace to biological systems. Reflecting the inherent nature of microfluidics and nanofluidics, the book includes as much interdisciplinary knowledge as possible. It provides the fundamental science background for newcomers and advanced techniques and concepts for experienced researchers and professionals

    Solid State Circuits Technologies

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    The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book
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