Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μm MOSFET's: A 3-D 'atomistic' simulation study

A three-dimensional (3-D) 'atomistic' simulation study of random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μm MOSFETs is presented. For the first time a systematic analysis of random dopant effects down to an individual dopant level was carried out in 3-D on a scale sufficient to provide quantitative statistical predictions. Efficient algorithms based on a single multigrid solution of the Poisson equation followed by the solution of a simplified current continuity equation are used in the simulations. The effects of various MOSFET design parameters, including the channel length and width, oxide thickness and channel doping, on the threshold voltage lowering and fluctuations are studied using typical samples of 200 atomistically different MOSFETs. The atomistic results for the threshold voltage fluctuations were compared with two analytical models based on dopant number fluctuations. Although the analytical models predict the general trends in the threshold voltage fluctuations, they fail to describe quantitatively the magnitude of the fluctuations. The distribution of the atomistically calculated threshold voltage and its correlation with the number of dopants in the channel of the MOSFETs was analyzed based on a sample of 2500 microscopically different devices. The detailed analysis shows that the threshold voltage fluctuations are determined not only by the fluctuation in the dopant number, but also in the dopant positio

Energy Efficient RF Transmitter Design using Enhanced Breakdown Voltage SOI-CMOS Compatible MESFETs

abstract: The high cut-off frequency of deep sub-micron CMOS technologies has enabled the integration of radio frequency (RF) transceivers with digital circuits. However, the challenging point is the integration of RF power amplifiers, mainly due to the low breakdown voltage of CMOS transistors. Silicon-on-insulator (SOI) metal semiconductor field effect transistors (MESFETs) have been introduced to remedy the limited headroom concern in CMOS technologies. The MESFETs presented in this thesis have been fabricated on different SOI-CMOS processes without making any change to the standard fabrication steps and offer 2-30 times higher breakdown voltage than the MOSFETs on the same process. This thesis explains the design steps of high efficiency and wideband RF transmitters using the proposed SOI-CMOS compatible MESFETs. This task involves DC and RF characterization of MESFET devices, along with providing a compact Spice model for simulation purposes. This thesis presents the design of several SOI-MESFET RF power amplifiers operating at 433, 900 and 1800 MHz with ~40% bandwidth. Measurement results show a peak power added efficiency (PAE) of 55% and a peak output power of 22.5 dBm. The RF-PAs were designed to operate in Class-AB mode to minimize the linearity degradation. Class-AB power amplifiers lead to poor power added efficiency, especially when fed with signals with high peak to average power ratio (PAPR) such as wideband code division multiple access (W-CDMA). Polar transmitters have been introduced to improve the efficiency of RF-PAs at backed-off powers. A MESFET based envelope tracking (ET) polar transmitter was designed and measured. A low drop-out voltage regulator (LDO) was used as the supply modulator of this polar transmitter. MESFETs are depletion mode devices; therefore, they can be configured in a source follower configuration to have better stability and higher bandwidth that MOSFET based LDOs. Measurement results show 350 MHz bandwidth while driving a 10 pF capacitive load. A novel polar transmitter is introduced in this thesis to alleviate some of the limitations associated with polar transmitters. The proposed architecture uses the backgate terminal of a partially depleted transistor on SOI process, which relaxes the bandwidth and efficiency requirements of the envelope amplifier in a polar transmitter. The measurement results of the proposed transmitter demonstrate more than three times PAE improvement at 6-dB backed-off output power, compared to the traditional RF transmitters.Dissertation/ThesisPh.D. Electrical Engineering 201

Semiconductor Device Modeling and Simulation for Electronic Circuit Design

This chapter covers different methods of semiconductor device modeling for electronic circuit simulation. It presents a discussion on physics-based analytical modeling approach to predict device operation at specific conditions such as applied bias (e.g., voltages and currents); environment (e.g., temperature, noise); and physical characteristics (e.g., geometry, doping levels). However, formulation of device model involves trade-off between accuracy and computational speed and for most practical operation such as for SPICE-based circuit simulator, empirical modeling approach is often preferred. Thus, this chapter also covers empirical modeling approaches to predict device operation by implementing mathematically fitted equations. In addition, it includes numerical device modeling approaches, which involve numerical device simulation using different types of commercial computer-based tools. Numerical models are used as virtual environment for device optimization under different conditions and the results can be used to validate the simulation models for other operating conditions

Use of spread spectrum time domain reflectometry to estimate state of health of power converters

pre-printA new online measurement and analysis method has been presented in this paper to identify the state of health of power converter circuits. Using spread spectrum time domain reflectometry (SSTDR), impedance in the various current paths inside the converter as well as any fault can be identified without interrupting the circuit's normal operation. Multiple sets of test data have been generated while the SSTDR process is applied to each of the components i.e. the power MOSFETs, the dc bus capacitor and the load. These obtained test data are analyzed to show how these test results are consistent with the impedances in various current paths. An impedance matrix was formed for a non-aged converter and a corresponding matrix using SSTDR data was formed as well. The matrices could be formed for any power converter, and the impedance matrix for the non-aged converter could be considered as a "Reference matrix" for comparison purpose. By comparing these two matrices, the variation in path impedances due to aging could be determined. This research aims to identify the measurable quantities to characterize the aging process, their origins of these quantities and propose convenient methods to measure them

Energy-efficient Wireless Analog Sensing for Persistent Underwater Environmental Monitoring

The design of sensors or "things" as part of the new Internet of Underwater Things (IoUTs) paradigm comes with multiple challenges including limited battery capacity, not polluting the water body, and the ability to track continuously phenomena with high temporal/spatial variability. We claim that traditional digital sensors are incapable to meet these demands because of their high power consumption, high complexity (cost), and the use of non-biodegradable materials. To address the above challenges, we propose a novel architecture consisting of a sensing substrate of dense analog biodegradable sensors over which lies the traditional Wireless Sensor Network (WSN). The substrate analog biodegradable sensors perform Shannon mapping (a data-compression technique) using just a single Field Effect Transistor (FET) without the need for power-hungry Analog-to-Digital Converters (ADCs) resulting in much lower power consumption, complexity, and the ability to be powered using only sustainable energy-harvesting techniques. A novel and efficient decoding technique is also presented. Both encoding/decoding techniques have been verified via Spice and MATLAB simulations accounting for underwater acoustic channel variations.Comment: 5 pages, IEEE UComms 201

Compact and Efficient Millimetre-Wave Circuits for Wideband Applications

Radio systems, along with the ever increasing processing power provided by computer technology, have altered many aspects of our society over the last century. Various gadgets and integrated electronics are found everywhere nowadays; many of these were science-fiction only a few decades ago. Most apparent is perhaps your ``smart phone'', possibly kept within arm's reach wherever you go, that provides various services, news updates, and social networking via wireless communications systems. The frameworks of the fifth generation wireless system is currently being developed worldwide. Inclusion of millimetre-wave technology promise high-speed piconets, wireless back-haul on pencil-beam links, and further functionality such as high-resolution radar imaging. This thesis addresses the challenge to provide signals at carrier frequencies in the millimetre-wave spectrum, and compact integrated transmitter front-ends of sub-wavelength dimensions. A radio frequency pulse generator, i.e. a ``wavelet genarator'', circuit is implemented using diodes and transistors in III--V compound semiconductor technology. This simple but energy-efficient front-end circuit can be controlled on the time-scale of picoseconds. Transmission of wireless data is thereby achieved at high symbol-rates and low power consumption per bit. A compact antenna is integrated with the transmitter circuit, without any intermediate transmission line. The result is a physically small, single-chip, transmitter front-end that can output high equivalent isotropically radiated power. This element radiation characteristic is wide-beam and suitable for array implementations

High efficiency smart voltage regulating module for green mobile computing

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.In this thesis a design for a smart high efficiency voltage regulating module capable of supplying the core of modern microprocessors incorporating dynamic voltage and frequency scaling (DVS) capability is accomplished using a RISC based microcontroller to facilitate all the functions required to control, protect, and supply the core with the required variable operating voltage as set by the DVS management system. Normally voltage regulating modules provide maximum power efficiency at designed peak load, and the efficiency falls off as the load moves towards lesser values. A mathematical model has been derived for the main converter and small signal analysis has been performed in order to determine system operation stability and select a control scheme that would improve converter operation response to transients and not requiring intense computational power to realize. A Simulation model was built using Matlab/Simulink and after experimenting with tuned PID controller and fuzzy logic controllers, a simple fuzzy logic control scheme was selected to control the pulse width modulated converter and several methods were devised to reduce the requirements for computational power making the whole system operation realizable using a low power RISC based microcontroller. The same microcontroller provides circuit adaptations operation in addition to providing protection to load in terms of over voltage and over current protection. A novel circuit technique and operation control scheme enables the designed module to selectively change some of the circuit elements in the main pulse width modulated buck converter so as to improve efficiency over a wider range of loads. In case of very light loads as the case when the device goes into standby, sleep or hibernation mode, a secondary converter starts operating and the main converter stops. The secondary converter adapts a different operation scheme using switched capacitor technique which provides high efficiency at low load currents. A fuzzy logic control scheme was chosen for the main converter for its lighter computational power requirement promoting implementation using ultra low power embedded controllers. Passive and active components were carefully selected to augment operational efficiency. These aspects enabled the designed voltage regulating module to operate with efficiency improvement in off peak load region in the range of 3% to 5%. At low loads as the case when the computer system goes to standby or sleep mode, the efficiency improvent is better than 13% which will have noticeable contribution in extending battery run time thus contributing to lowering the carbon footprint of human consumption

Quantifying device degradation in live power converters using SSTDR assisted impedance Matrix

pre-printA noninterfering measurement technique designed around spread spectrum time domain reflectometry (SSTDR) has been proposed in this paper to identify the level of aging associated with power semiconductor switches inside a live converter circuit. Power MOSFETs are one of the most age-sensitive components in power converter circuits, and this paper demonstrates how SSTDR can be used to determine the characteristic degradation of the switching MOSFETs used in various power converters. An SSTDR technique was applied to determine the aging in power MOSFETs, while they remained energized in live circuits. In addition, SSTDR was applied to various test nodes of an H-bridge ac-ac converter, and multiple impedance matrices were created based on the measured reflections. An error minimization technique has been developed to locate and determine the origin and amount of aging in this circuit, and this technique provides key information about the level of aging associated to the components of interest. By conducting component level failure analysis, the overall reliability of an H-bridge ac-ac converter has been derived and incorporated in this paper