A Sub-µW Reconfigurable Front-End for Invasive Neural Recording

This paper presents a sub-μW ac-coupled reconfigurable front-end for the purpose of neural recording. The proposed topology embeds in it filtering capabilities allowing it to select among different frequency bands inside the neural signal spectrum. Power consumption is optimized by designing for bandwidth-specific noise targets that take into account the spectral characteristics of the input signal as well as the noise bandwidths of the noise generators in the circuit itself. An experimentally verified prototype designed in a 180 nm CMOS process draws a maximum of 815 nW from a 1 V source. The measured input-referred spot-noise at 500 Hz is 75 nV/√Hz while the integrated noise in the 200 Hz - 5 kHz band is 4.1 μVrms.Ministerio de Economía y Competitividad TEC2016-80923- PJunta de Andalucía TIC 233

A Powerful Optimization Tool for Analog Integrated Circuits Design

This paper presents a new optimization tool for analog circuit design. Proposed tool is based on the robust version of the differential evolution optimization method. Corners of technology, temperature, voltage and current supplies are taken into account during the optimization. That ensures robust resulting circuits. Those circuits usually do not need any schematic change and are ready for the layout.. The newly developed tool is implemented directly to the Cadence design environment to achieve very short setup time of the optimization task. The design automation procedure was enhanced by optimization watchdog feature. It was created to control optimization progress and moreover to reduce the search space to produce better design in shorter time. The optimization algorithm presented in this paper was successfully tested on several design examples

On the suitability and development of layout templates for analog layout reuse and layout-aware synthesis

Accelerating the synthesis of increasingly complex analog integrated circuits is key to bridge the widening gap between what we can integrate and what we can design while meeting ever-tightening time-to-market constraints. It is a well-known fact in the semiconductor industry that such goal can only be attained by means of adequate CAD methodologies, techniques, and accompanying tools. This is particularly important in analog physical synthesis (a.k.a. layout generation), where large sensitivities of the circuit performances to the many subtle details of layout implementation (device matching, loading and coupling effects, reliability, and area features are of utmost importance to analog designers), render complete automation a truly challenging task. To approach the problem, two directions have been traditionally considered, knowledge-based and optimization-based, both with their own pros and cons. Besides, recently reported solutions oriented to speed up the overall design flow by means of reuse-based practices or by cutting off time-consuming, error-prone spins between electrical and layout synthesis (a technique known as layout-aware synthesis), rely on a outstandingly rapid yet efficient layout generation method. This paper analyses the suitability of procedural layout generation based on templates (a knowledge-based approach) by examining the requirements that both layout reuse and layout-aware solutions impose, and how layout templates face them. The ability to capture the know-how of experienced layout designers and the turnaround times for layout instancing are considered main comparative aspects in relation to other layout generation approaches. A discussion on the benefit-cost trade-off of using layout templates is also included. In addition to this analysis, the paper delves deeper into systematic techniques to develop fully reusable layout templates for analog circuits, either for a change of the circuit sizing (i.e., layout retargeting) or a change of the fabrication process (i.e., layout migration). Several examples implemented with the Cadence's Virtuoso tool suite are provided as demonstration of the paper's contributions.Ministerio de Educación y Ciencia TEC2004-0175

Modeling of thermally induced skew variations in clock distribution network

Clock distribution network is sensitive to large thermal gradients on the die as the performance of both clock buffers and interconnects are affected by temperature. A robust clock network design relies on the accurate analysis of clock skew subject to temperature variations. In this work, we address the problem of thermally induced clock skew modeling in nanometer CMOS technologies. The complex thermal behavior of both buffers and interconnects are taken into account. In addition, our characterization of the temperature effect on buffers and interconnects provides valuable insight to designers about the potential impact of thermal variations on clock networks. The use of industrial standard data format in the interface allows our tool to be easily integrated into existing design flow

An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics

Near-sensor data analytics is a promising direction for IoT endpoints, as it minimizes energy spent on communication and reduces network load - but it also poses security concerns, as valuable data is stored or sent over the network at various stages of the analytics pipeline. Using encryption to protect sensitive data at the boundary of the on-chip analytics engine is a way to address data security issues. To cope with the combined workload of analytics and encryption in a tight power envelope, we propose Fulmine, a System-on-Chip based on a tightly-coupled multi-core cluster augmented with specialized blocks for compute-intensive data processing and encryption functions, supporting software programmability for regular computing tasks. The Fulmine SoC, fabricated in 65nm technology, consumes less than 20mW on average at 0.8V achieving an efficiency of up to 70pJ/B in encryption, 50pJ/px in convolution, or up to 25MIPS/mW in software. As a strong argument for real-life flexible application of our platform, we show experimental results for three secure analytics use cases: secure autonomous aerial surveillance with a state-of-the-art deep CNN consuming 3.16pJ per equivalent RISC op; local CNN-based face detection with secured remote recognition in 5.74pJ/op; and seizure detection with encrypted data collection from EEG within 12.7pJ/op.Comment: 15 pages, 12 figures, accepted for publication to the IEEE Transactions on Circuits and Systems - I: Regular Paper

CMOS-3D smart imager architectures for feature detection

This paper reports a multi-layered smart image sensor architecture for feature extraction based on detection of interest points. The architecture is conceived for 3-D integrated circuit technologies consisting of two layers (tiers) plus memory. The top tier includes sensing and processing circuitry aimed to perform Gaussian filtering and generate Gaussian pyramids in fully concurrent way. The circuitry in this tier operates in mixed-signal domain. It embeds in-pixel correlated double sampling, a switched-capacitor network for Gaussian pyramid generation, analog memories and a comparator for in-pixel analog-to-digital conversion. This tier can be further split into two for improved resolution; one containing the sensors and another containing a capacitor per sensor plus the mixed-signal processing circuitry. Regarding the bottom tier, it embeds digital circuitry entitled for the calculation of Harris, Hessian, and difference-of-Gaussian detectors. The overall system can hence be configured by the user to detect interest points by using the algorithm out of these three better suited to practical applications. The paper describes the different kind of algorithms featured and the circuitry employed at top and bottom tiers. The Gaussian pyramid is implemented with a switched-capacitor network in less than 50 μs, outperforming more conventional solutions.Xunta de Galicia 10PXIB206037PRMinisterio de Ciencia e Innovación TEC2009-12686, IPT-2011-1625-430000Office of Naval Research N00014111031

ANALYSIS OF MOS CURRENT MODE LOGIC (MCML) AND IMPLEMENTATION OF MCML STANDARD CELL LIBRARY FOR LOW-NOISE DIGITAL CIRCUIT DESIGN

MOS current mode logic (MCML) offers low noise digital circuits that reduce noise that can cripple analog components in mixed-signal integrated circuits, when compared to CMOS digital circuits. An MCML standard cell library was developed for the Cadence Virtuoso Integrated Circuit (IC) design software that gives IC designers the ability to design complex, low noise digital circuits for use in mixed-signal and noise sensitive systems at a high level of abstraction, allowing them to get superior products to market faster than competitors. The MCML standard cell library developed and presented here allows for fast development of mixed signal circuits by providing quiet digital building block gates that reduce the simultaneous switching noise (SSN) by an order of magnitude over conventional CMOS based designs [3]. This thesis project developed the following digital gates in MCML as a standard cell library for general-purpose low noise and very low noise applications: inverter, buffer, NAND, AND, NOR, OR, XOR, NXOR, 2:1 MUX, CMOS to MCML, MCML to CMOS, and double edge triggered flip-flop (DETFF)

ASIC para estimulação elétrica da espinal medula

Spinal Cord Injuries (SCI) have severe consequences such as tetraplegia and paraplegia, which dramatically affect the healthcare of the patients. Successful therapies for such injuries are yet to be attainable. Currently, there is a focus on the study and implementation of small implantable devices that are capable of providing in-vivo electrical stimulation to the spinal cord. Since the impedance of the neural tissue experiences constant changes, the focus is on using current stimulation instead of voltage, to compensate the impedance variations. Furthermore, the usage of scaffolds to provide alignment on the regrown fibers, combined with electrical stimulation is viewed as possible solution for SCI therapy. The NeuroStim- Spinal project, in which this work is inserted, aims to propose a SCI therapy based on in-vivo electrical stimulation combined with 3D printed scaffolds that have in its composition based materials (GBM) and adipose derived decellularized tissue (adECM). The work presented is an application-specific integrated circuit design (ASIC) that provides current-mode stimulation for neuronal regeneration, with the objective of providing in-vivo electrical stimulation for SCI therapy. The main challenges on the design of such devices is in obtaining low circuit area and power consumption, while maintaining the specifications needed. These characteristics are important, since it is intended to be an implantable device. The stimulation circuit consists of, a communication interface with a microcontroller using the Serial Peripheral Communication (SPI) protocol, a 10-bit DAC (Digital-to-Analog Converter) based on a binary charge scaling architecture, a voltage-to-current converter with a feed-forward voltage attenuator (FFVA) architecture, and a H-bridge circuit composed of CMOS switches to drive the scaffold. Results demonstrate that the system developed is capable of driving current from 0 to 200μA with an absolute error bellow 0.75μA. In addition, the developed circuit can provide these range of currents with high linearity to a 15k load impedance. The system can still provide linear stimulation for higher load impedance’s, but in smaller current ranges. Furthermore, the circuit uses a supply voltage of 5V and has an average power dissipation of 19.5mW. The ASIC was developed using a 0.35μm CMOS technology, has dimensions of 270μm per 700μm, which corresponds to a total area of 0.19mm2. The work was developed using the Cadence software.Lesões na Medula Espinhal são causadas sobretudo devido acidentes rodoviários, quedas e lesões na prática de desportos. Estas têm graves consequências no estado de saúde dos pacientes, uma vez que saõ responsáveis por diagnósticos como tetraplegia e paraplegia. Até hoje, terapias eficazes para este tipo de lesões ainda não foram conseguidas, o que torna esta temática num foco de estudo. Atualmente, uma das orientações deste foco de estudo está direcionado em dispositivos elétricos implantáveis capazes de estimular a espinal medula in-vivo, promovendo a regeneração da mesma. Adicionalmente, o uso de materiais (scaffolds) que permitem manter o alinhemento no crescimento das fibras, em conjunto com estimulação elétrica é vista como a solução consensual para terapias relacionadas com Lesões na Medula Espinhal. Assim, o projeto NeuroStimSpinal, na qual este trabalho se insere, foi proposto. Este tem como objetivo propor uma terapia para esta problemática usando estimulação elétrica em conjunto com scaffolds impressas em 3D. O trabalho apresentado nesta dissertação é baseado num circuito integrado de aplicação específica (CIAE) para estimulação em corrente da espinal medula, com o intuito de promover a regeneração da mesma. Os desafios na implementação deste tipo de circuitos estão relacionados com a necessidade destes terem de ser pequenos em tamanho e consumir uma potência reduzida, mantendo as características necessárias para a estimulação, uma vez que é necessário que o mesmo faça parte de um dispositivo implantável. O circuito de estimulação proposto consiste: numa interface de comunicação com a unidade de controlo (microcontrolador) usando o protocolo Serial Peripheral Communication (SPI); um conversor digital para analógico de 10 bits, o qual se baseia numa arquitetura de escalonamento binário por carga; um conversor tensão para corrente rail-to-rail e uma ponte H que direciona a corrente pela scaffold, cuja implementação se baseia no uso de portas de transmissão como comutadores. Resultados ao trabalho desenvolvido mostram que o circuito é capaz de estimular a scaffold com correntes entre 0 to 200μA com um erro na corrente de estimulação inferior a 0.75μA. O circuito é capaz ainda de fornecer uma corrente linear, na gama mencionada, a cargas com impedancias até 15k . Para cargas superiores o circuito é capaz de fornecer uma corrente linear, embora em gamas de correntes menores. O circuito implementado usa como tensão de alimentação 5V, tem um consumo médio de potência de 19.5mW e ocupa uma área de 0.19mm2. No decurso do trabalho desenvolvido foi utilizada uma tecnlogoia CMOS de 0.35um. A implementação e resultados foram obtidos com recurso ao software Cadence.Mestrado em Engenharia Eletrónica e Telecomunicaçõe

On Complexity, Energy- and Implementation-Efficiency of Channel Decoders

Future wireless communication systems require efficient and flexible baseband receivers. Meaningful efficiency metrics are key for design space exploration to quantify the algorithmic and the implementation complexity of a receiver. Most of the current established efficiency metrics are based on counting operations, thus neglecting important issues like data and storage complexity. In this paper we introduce suitable energy and area efficiency metrics which resolve the afore-mentioned disadvantages. These are decoded information bit per energy and throughput per area unit. Efficiency metrics are assessed by various implementations of turbo decoders, LDPC decoders and convolutional decoders. New exploration methodologies are presented, which permit an appropriate benchmarking of implementation efficiency, communications performance, and flexibility trade-offs. These exploration methodologies are based on efficiency trajectories rather than a single snapshot metric as done in state-of-the-art approaches.Comment: Submitted to IEEE Transactions on Communication