Custom architecture for multicore audio Beamforming systems

The audio Beamforming (BF) technique utilizes microphone arrays to extract acoustic sources recorded in a noisy environment. In this article, we propose a new approach for rapid development of multicore BF systems. Research on literature reveals that the majority of such experimental and commercial audio systems are based on desktop PCs, due to their high-level programming support and potential of rapid system development. However, these approaches introduce performance bottlenecks, excessive power consumption, and increased overall cost. Systems based on DSPs require very low power, but their performance is still limited. Custom hardware solutions alleviate the aforementioned drawbacks, however, designers primarily focus on performance optimization without providing a high-level interface for system control and test. In order to address the aforementioned problems, we propose a custom platform-independent architecture for reconfigurable audio BF systems. To evaluate our proposal, we implement our architecture as a heterogeneous multicore reconfigurable processor and map it onto FPGAs. Our approach combines the software flexibility of General-Purpose Processors (GPPs) with the computational power of multicore platforms. In order to evaluate our system we compare it against a BF software application implemented to a low-power Atom 330, amiddle-ranged Core2 Duo, and a high-end Core i3. Experimental results suggest that our proposed solution can extract up to 16 audio sources in real time under a 16-microphone setup. In contrast, under the same setup, the Atom 330 cannot extract any audio sources in real time, while the Core2 Duo and the Core i3 can process in real time only up to 4 and 6 sources respectively. Furthermore, a Virtex4-based BF system consumes more than an order less energy compared to the aforementioned GPP-based approaches. © 2013 ACM

GPU Integration into a Software Defined Radio Framework

Software Defined Radio (SDR) was brought about by moving processing done on specific hardware components to reconfigurable software. Hardware components like General Purpose Processors (GPPs), Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs) are used to make the software and hardware processing of the radio more portable and as efficient as possible. Graphics Processing Units (GPUs) designed years ago for video rendering, are now finding new uses in research. The parallel architecture provided by the GPU gives developers the ability to speed up the performance of computationally intense programs. An open source tool for SDR, Open Source Software Communications Architecture (SCA) Implementation: Embedded (OSSIE), is a free waveform development environment for any developer who wants to experiment with SDR. In this work, OSSIE is integrated with a GPU computing framework to show how performance improvement can be gained from GPU parallelization. GPU research performed with SDR encompasses improving SDR simulations to implementing specific wireless protocols. In this thesis, we are aiming to show performance improvement within an SCA architected SDR implementation. The software components within OSSIE gained significant performance increases with little software changes due to the natural parallelism of the GPU, using Compute Unified Device Architecture (CUDA), Nvidia\u27s GPU programming API. Using sample data sizes for the I and Q channel inputs, performance improvements were seen in as little as 512 samples when using the GPU optimized version of OSSIE. As the sample size increased, the CUDA performance improved as well. Porting OSSIE components onto the CUDA architecture showed that improved performance can be seen in SDR related software through the use of GPU technology

Studies on Implementation of . . . High Throughput and Low Power Consumption

In this thesis we discuss design and implementation of frequency selective digital filters with high throughput and low power consumption. The thesis includes proposed arithmetic transformations of lattice wave digital filters that aim at increasing the throughput and reduce the power consumption of the filter implementation. The thesis also includes two case studies where digital filters with high throughput and low power consumption are required. A method for obtaining high throughput as well as reduced power consumption of digital filters is arithmetic transformation of the filter structure. In this thesis arithmetic transformations of first- and second-order Richards’ allpass sections composed by symmetric two-port adaptors and implemented using carry-save arithmetic are proposed. Such filter sections can be used for implementation of lattice wave digital filters and bireciprocal lattice wave digital filters. The latter structures are efficient for implementation of interpolators and decimators by factors of two. Th

Bit-stream adders and multipliers for tri-level sigma-delta modulators

We propose both adder and multiplier circuits for bit-stream signal processing customized for tri-level sigma-delta modulated signals. These architectures are the 2-bit extensions from the existing 1-bit bit-stream adders and multipliers, and are shown to offer better signal-to-noise performance. Field-programmable gate array implementations then confirm their efficacy. © 2007 IEEE.published_or_final_versio

Compression Of 2-Tone Manuscript For Multimedia Application [QA76.9.D33 B171 2008 f rb].

Malaysia seperti negara lain kaya dengan dokumen lama berlandaskan unsur sejarah dan kebudayaan yang jarang ditemui. Malaysia like any other country has old and rare documents that depict its history and culture

Multi-dimensional filter design in digital television systems

Imperial Users onl

Switched-current filtering systems: design, synthesis and software development

Allpass filters are commonly employed in many applications to perform group delay equalisation in the passband. They are non-minimum phase by definition and are characterised by poles and zeros in mirror-image symmetry. SI allpass filters of both cascade biquad and bilinear-LDI ladder types have been in existence. These were implemented using Euler based integrators. Cascade biquads are known to have highly sensitive amplitude responses and Euler integrators suffer from excess phase. The equalisers that are proposed here are based on bilinear integrators instead of Euler ones. Derivation of these equalisers can proceed from either the s-domain, or directly from the z-domain, where a prototype is synthesised using the respective continued-fractions expansions, and simulated using standard matrix methods. The amplitude response of the bilinear allpass filter is shown to be completely insensitive to deviations in the reactive ladder section. Simulations of sensitivities and non-ideal responses reveal the advantages and disadvantages of the various structures. Existing DI multirate filters have to date been implemented as direct-form FIR and IIR polyphase structures, or as simple cascade biquad or ladder structures with non-optimum settling times. FIR structures require a large number of impulse coefficients to realise highly selective responses. Even in the case of linear phase response with symmetric impulse coefficients, when the number of coefficients can be halved, significant overheads can be incurred by additional multiplexing circuitry. Direct-form IIR structures are simple but are known to be sensitive to coefficient deviations and structures with non-optimum settling times operate entirely at the higher clock frequency. The novel SI decimators and interpolators proposed are based on low sensitivity ladder structures coupled with FIR polyphase networks. They operate entirely at the lower clock frequency which maximises the time available for the memory cells to settle. Two different coupling architectures with different advantages and disadvantages are studied

Applications of Lattice Filters to Quadrature Mirror Filter Banks

Presented is a method for designing and implementing lattice filters to be used in Quadrature Mirror Filter (QMF) Banks. Quadrature Mirror Filter Banks find use in applications where a signal must be spilt into subbands operated on then reconstructed in the output. Because of their structure, lattice filters do this very well and allow perfect reconstruction, even when the lattice coefficients must be quantized. In this paper QMF\u27s and Lattice Filters are derived and analyzed. Application of the lattice filter is presented along with a design program and example of its use to implement a QMF. The computer aided design procedure allows the user to input the stop-band frequency, normalized to the sampling frequency, and the desired attenuation. The resulting outputs are the lattice coefficients, and the Finite Impulse Response (FIR) coefficients of an FIR filter having the same characteristics. The program selects a set of coefficients based on optimal coefficients that are within the desired tolerance. The filter design program was written in FORTRAN, with the filter coefficients stored in a data file on disk. Programs were written in MATHCAD© to show the lattice filter response and to simulate the QMF using these coefficients

Application of multirate digital signal processing to image compression

With the increasing emphasis on digital communication and digital processing of images and video, image compression is drawing considerable interest as a means of reducing computer storage and communication channels bandwidth requirements. This thesis presents a method for the compression of grayscale images which is based on the multirate digital signal processing system. The input image spectrum is decomposed into octave wide subbands by critically resampling and filtering the image using separable FIR digital filters. These filters are chosen to satisfy the perfect reconstruction requirement. Simulation results on rectangularly sampled images (including a text image) are presented. Then, the algorithm is applied to the hexagonally resampled images and the results show a slight increase in the compression efficiency. Comparing the results against the standard (JPEG), indicate that this method does not have the blocking effect of JPEG and it preserves the edges even in the presence of high noise level