Accurate a priori signal integrity estimation using a multilevel dynamic interconnect model for deep submicron VLSI design.

A multilevel dynamic interconnect model was derived for accurate a priori signal integrity estimates. Cross-talk and delay estimations over interconnects in deep submicron technology were analyzed systematically using this model. Good accuracy and excellent time-efficiency were found compared with electromagnetic simulations. We aim to build a dynamic interconnect library with this model to facilitate the interconnect issues for future VLSI design

A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects

Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm^2

Coherent terabit communications with microresonator Kerr frequency combs

Optical frequency combs enable coherent data transmission on hundreds of wavelength channels and have the potential to revolutionize terabit communications. Generation of Kerr combs in nonlinear integrated microcavities represents a particularly promising option enabling line spacings of tens of GHz, compliant with wavelength-division multiplexing (WDM) grids. However, Kerr combs may exhibit strong phase noise and multiplet spectral lines, and this has made high-speed data transmission impossible up to now. Recent work has shown that systematic adjustment of pump conditions enables low phase-noise Kerr combs with singlet spectral lines. Here we demonstrate that Kerr combs are suited for coherent data transmission with advanced modulation formats that pose stringent requirements on the spectral purity of the optical source. In a first experiment, we encode a data stream of 392 Gbit/s on subsequent lines of a Kerr comb using quadrature phase shift keying (QPSK) and 16-state quadrature amplitude modulation (16QAM). A second experiment shows feedback-stabilization of a Kerr comb and transmission of a 1.44 Tbit/s data stream over a distance of up to 300 km. The results demonstrate that Kerr combs can meet the highly demanding requirements of multi-terabit/s coherent communications and thus offer a solution towards chip-scale terabit/s transceivers

Improving the Convergence of Vector Fitting for Equivalent Circuit Extraction From Noisy Frequency Responses

The vector fitting (VF) algorithm has become a common tool in electromagnetic compatibility and signal integrity studies. This algorithm allows the derivation of a rational approximation to the transfer matrix of a given linear structure starting from measured or simulated frequency responses. This paper addresses the convergence properties of a VF when the frequency samples are affected by noise.We show that small amounts of noise can seriously impair or destroy convergence. This is due to the presence of spurious poles that appear during the iterations. To overcome this problem we suggest a simple modification of the basic VF algorithm, based on the identification and removal of the spurious poles. Also, an incremental pole addition and relocation process is proposed in order to provide automatic order estimation even in the presence of significant noise.We denote the resulting algorithm as vector fitting with adding and skimming (VF-AS). A thorough validation of the VF-AS algorithm is presented using a Monte Carlo analysis on synthetic noisy frequency responses. The results show excellent convergence and significant improvements with respect to the basic VF iteration scheme. Finally, we apply the new VF-AS algorithm to measured scattering responses of interconnect structures and networks typical of high-speed digital systems

Design and modelling of variability tolerant on-chip communication structures for future high performance system on chip designs

The incessant technology scaling has enabled the integration of functionally complex System-on-Chip (SoC) designs with a large number of heterogeneous systems on a single chip. The processing elements on these chips are integrated through on-chip communication structures which provide the infrastructure necessary for the exchange of data and control signals, while meeting the strenuous physical and design constraints. The use of vast amounts of on chip communications will be central to future designs where variability is an inherent characteristic. For this reason, in this thesis we investigate the performance and variability tolerance of typical on-chip communication structures. Understanding of the relationship between variability and communication is paramount for the designers; i.e. to devise new methods and techniques for designing performance and power efficient communication circuits in the forefront of challenges presented by deep sub-micron (DSM) technologies. The initial part of this work investigates the impact of device variability due to Random Dopant Fluctuations (RDF) on the timing characteristics of basic communication elements. The characterization data so obtained can be used to estimate the performance and failure probability of simple links through the methodology proposed in this work. For the Statistical Static Timing Analysis (SSTA) of larger circuits, a method for accurate estimation of the probability density functions of different circuit parameters is proposed. Moreover, its significance on pipelined circuits is highlighted. Power and area are one of the most important design metrics for any integrated circuit (IC) design. This thesis emphasises the consideration of communication reliability while optimizing for power and area. A methodology has been proposed for the simultaneous optimization of performance, area, power and delay variability for a repeater inserted interconnect. Similarly for multi-bit parallel links, bandwidth driven optimizations have also been performed. Power and area efficient semi-serial links, less vulnerable to delay variations than the corresponding fully parallel links are introduced. Furthermore, due to technology scaling, the coupling noise between the link lines has become an important issue. With ever decreasing supply voltages, and the corresponding reduction in noise margins, severe challenges are introduced for performing timing verification in the presence of variability. For this reason an accurate model for crosstalk noise in an interconnection as a function of time and skew is introduced in this work. This model can be used for the identification of skew condition that gives maximum delay noise, and also for efficient design verification