42,331 research outputs found
Motion estimation based frame rate conversion hardware designs
Frame Rate Up-Conversion (FRC) is the conversion of a lower frame rate video signal to a higher frame rate video signal. FRC algorithms using Motion Estimation (ME) obtain better quality results. Among the block matching ME algorithms, Full Search (FS) achieves the best performance since it searches all search locations in a given search range. However, its computational complexity, especially for the recently available High Definition (HD) video formats, is very high. Therefore, in this thesis, we proposed new ME algorithms for real-time processing of HD video and designed efficient hardware architectures for implementing these ME algorithms. These algorithms perform very close to FS by searching much fewer search locations than FS algorithm. We implemented the proposed hardware architectures in VHDL and mapped them to a Xilinx FPGA. ME for FRC requires finding the true motion among consecutive frames. In order to find the true motion, Vector Median Filter (VMF) is used to smooth the motion vector field obtained by block matching ME. However, VMFs are difficult to implement in real-time due to their high computational complexity. Therefore, in this thesis, we proposed several techniques to reduce the computational complexity of VMFs by using data reuse methodology and by exploiting the spatial correlations in the vector field. In addition, we designed an efficient VMF hardware including the computation reduction techniques exploiting the spatial correlations in the motion vector field. We implemented the proposed hardware architecture in Verilog and mapped it to a Xilinx FPGA. ME based FRC requires interpolation of frames using the motion vectors found by ME. Frame interpolation algorithms also have high computational complexity. Therefore, in this thesis, we proposed a low cost hardware architecture for real-time implementation of frame interpolation algorithms. The proposed hardware architecture is reconfigurable and it allows adaptive selection of frame interpolation algorithms for each Macroblock. We implemented the proposed hardware architecture in VHDL and mapped it to a low cost Xilinx FPGA
Asynchronous spiking neurons, the natural key to exploit temporal sparsity
Inference of Deep Neural Networks for stream signal (Video/Audio) processing in edge devices is still challenging. Unlike the most state of the art inference engines which are efficient for static signals, our brain is optimized for real-time dynamic signal processing. We believe one important feature of the brain (asynchronous state-full processing) is the key to its excellence in this domain. In this work, we show how asynchronous processing with state-full neurons allows exploitation of the existing sparsity in natural signals. This paper explains three different types of sparsity and proposes an inference algorithm which exploits all types of sparsities in the execution of already trained networks. Our experiments in three different applications (Handwritten digit recognition, Autonomous Steering and Hand-Gesture recognition) show that this model of inference reduces the number of required operations for sparse input data by a factor of one to two orders of magnitudes. Additionally, due to fully asynchronous processing this type of inference can be run on fully distributed and scalable neuromorphic hardware platforms
Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding
Real-time and high-quality video coding is gaining a wide interest in the research and industrial community for different applications. H.264/AVC, a recent standard for high performance video coding, can be successfully exploited in several scenarios including digital video broadcasting, high-definition TV and DVD-based systems, which require to sustain up to tens of Mbits/s. To that purpose this paper proposes optimized architectures for H.264/AVC most critical tasks, Motion estimation and context adaptive binary arithmetic coding. Post synthesis results on sub-micron CMOS standard-cells technologies show that the proposed architectures can actually process in real-time 720 Ă— 480 video sequences at 30 frames/s and grant more than 50 Mbits/s. The achieved circuit complexity and power consumption budgets are suitable for their integration in complex VLSI multimedia systems based either on AHB bus centric on-chip communication system or on novel Network-on-Chip (NoC) infrastructures for MPSoC (Multi-Processor System on Chip
Low Power Depth Estimation of Rigid Objects for Time-of-Flight Imaging
Depth sensing is useful in a variety of applications that range from
augmented reality to robotics. Time-of-flight (TOF) cameras are appealing
because they obtain dense depth measurements with minimal latency. However, for
many battery-powered devices, the illumination source of a TOF camera is power
hungry and can limit the battery life of the device. To address this issue, we
present an algorithm that lowers the power for depth sensing by reducing the
usage of the TOF camera and estimating depth maps using concurrently collected
images. Our technique also adaptively controls the TOF camera and enables it
when an accurate depth map cannot be estimated. To ensure that the overall
system power for depth sensing is reduced, we design our algorithm to run on a
low power embedded platform, where it outputs 640x480 depth maps at 30 frames
per second. We evaluate our approach on several RGB-D datasets, where it
produces depth maps with an overall mean relative error of 0.96% and reduces
the usage of the TOF camera by 85%. When used with commercial TOF cameras, we
estimate that our algorithm can lower the total power for depth sensing by up
to 73%
On evolution of CMOS image sensors
CMOS Image Sensors have become the principal technology in majority of digital cameras. They started replacing the film and Charge Coupled Devices in the last decade with the promise of lower cost, lower power requirement, higher integration and the potential of focal plane processing. However, the principal factor behind their success has been the ability to utilise the shrinkage in CMOS technology to make smaller pixels, and thereby have more resolution without increasing the cost. With the market of image sensors exploding courtesy their inte- gration with communication and computation devices, technology developers improved the CMOS processes to have better optical performance. Nevertheless, the promises of focal plane processing as well as on-chip integration have not been fulfilled. The market is still being pushed by the desire of having higher number of pixels and better image quality, however, differentiation is being difficult for any image sensor manufacturer. In the paper, we will explore potential disruptive growth directions for CMOS Image sensors and ways to achieve the same
MIMO Transmission with Residual Transmit-RF Impairments
Physical transceiver implementations for multiple-input multiple-output
(MIMO) wireless communication systems suffer from transmit-RF (Tx-RF)
impairments. In this paper, we study the effect on channel capacity and
error-rate performance of residual Tx-RF impairments that defy proper
compensation. In particular, we demonstrate that such residual distortions
severely degrade the performance of (near-)optimum MIMO detection algorithms.
To mitigate this performance loss, we propose an efficient algorithm, which is
based on an i.i.d. Gaussian model for the distortion caused by these
impairments. In order to validate this model, we provide measurement results
based on a 4-stream Tx-RF chain implementation for MIMO orthogonal
frequency-division multiplexing (OFDM).Comment: to be presented at the International ITG Workshop on Smart Antennas -
WSA 201
Spiking neural networks trained with backpropagation for low power neuromorphic implementation of voice activity detection
Recent advances in Voice Activity Detection (VAD) are driven by artificial
and Recurrent Neural Networks (RNNs), however, using a VAD system in
battery-operated devices requires further power efficiency. This can be
achieved by neuromorphic hardware, which enables Spiking Neural Networks (SNNs)
to perform inference at very low energy consumption. Spiking networks are
characterized by their ability to process information efficiently, in a sparse
cascade of binary events in time called spikes. However, a big performance gap
separates artificial from spiking networks, mostly due to a lack of powerful
SNN training algorithms. To overcome this problem we exploit an SNN model that
can be recast into an RNN-like model and trained with known deep learning
techniques. We describe an SNN training procedure that achieves low spiking
activity and pruning algorithms to remove 85% of the network connections with
no performance loss. The model achieves state-of-the-art performance with a
fraction of power consumption comparing to other methods.Comment: 5 pages, 2 figures, 2 table
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